Semiconductor device

A semiconductor device, comprising:

• a first impurity region on a substrate;
• a plurality of channel patterns protruding from an upper surface of the substrate, each of the channel patterns extending in a first direction substantially parallel to an upper surface of the substrate and being arranged in a second direction perpendicular to the first direction;
• second impurity regions covering an entire upper surface of each of the plurality of channel patterns;
• a gate structure on sidewalls of the channel patterns and the substrate between the channel patterns, the gate structure comprising a gate insulation pattern and a gate electrode;
• a first contact pattern contacting entire upper surfaces of the second impurity regions and extending in the second direction between adjacent ones of the second impurity regions;
• a second contact pattern contacting a surface of the gate electrode;
• and
• a spacer between the first and second contact patterns and between a sidewall of the second contact pattern and a portion of the gate structure on the sidewalls of the channel patterns,
• wherein the spacer completely surrounds an entire sidewall of the second contact pattern, the first contact pattern completely surrounds the second contact pattern in plan view, the spacer contacts the portion of the gate structure on the sidewalls of the channel patterns and contacts a sidewall of each of the first and second contact patterns, and the first and second contact patterns are electrically isolated by the spacer, and
• wherein the second contact pattern extends through a portion of the first contact pattern.

A semiconductor device, comprising:

• a first impurity region on a substrate;
• a plurality of channel patterns protruding from an upper surface of the substrate, each of the channel patterns extending in a first direction substantially parallel to an upper surface of the substrate;
• second impurity regions covering an entire upper surface of respective ones of the plurality of channel patterns;
• a gate structure on a sidewall of each of the channel patterns and the substrate between the channel patterns, the gate structure comprising a gate insulation pattern and a gate electrode;
• a first contact pattern contacting entire upper surfaces of the second impurity regions, the first contact pattern covering upper surfaces of the second impurity regions and extending between adjacent ones of the second impurity regions;
• a second contact pattern contacting a surface of the gate electrode;
• and
• a spacer completely surrounding an entire sidewall of the second contact pattern,
• wherein the first contact pattern completely surrounds the second contact pattern in plan view, the spacer covers a sidewall of the first contact pattern and a sidewall of each of the second impurity regions, the spacer contacts a portion of the gate structure on the sidewalls of the channel patterns and contacts a sidewall of each of the first and second contact patterns, and
• wherein the second contact pattern extends through a portion of the first contact pattern.