Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSheng-Kai Su
Life of this patent
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Abstract
A semiconductor device includes a substrate, a gate structure, semimetallic source/drain structures, and source/drain contacts. The gate structure is over the substrate. The semimetallic source/drain structures are respectively on opposite sides of the gate structure, in which a band structure of each of the semimetallic source/drain structures has a valence band and a conduction band at different symmetry k-points. The source/drain contacts land on top surfaces of the semimetallic source/drain structures, respectively.
Claims20
A semiconductor device, comprising:
- a gate structure over a substrate and having a gate electrode and a gate dielectric cupping an underside of the gate electrode;
- gate spacers on opposite sidewalls of the gate structure;
- semimetallic source/drain structures respectively on opposite sides of the gate structure, wherein a band structure of each of the semimetallic source/drain structures has a valence band and a conduction band at different symmetry k-points, and wherein bottom surfaces of the semimetallic source/drain structures are lower than bottom surfaces of the gate spacers;
- an interlayer dielectric (ILD) layer on sides of the gate structure, wherein portions of the semimetallic source/drain structures are in the ILD layer and in contact with sidewalls of the ILD layer;
- and
- source/drain contacts landing on top surfaces of the semimetallic source/drain structures, respectively, interfaces of the semimetallic source/drain structures and the source/drain contacts are in a position higher than a bottom surface of the gate electrode.
A semiconductor device, comprising:
- a gate structure over a substrate;
- gate spacers respectively on opposite sidewalls of the gate structure;
- a first 2D material layer extending between the gate structure and the substrate, wherein the first 2D material layer is in contact with an entirety of a bottom surface of the gate structure;
- a second 2D material layer having a first portion laterally extending from the first 2D material layer and under the gate spacers, and a second portion laterally extending from the first portion to beyond the gate spacers;
- a third 2D material layer over the second portion of the second 2D material layer and made of a same material as the second 2D material layer, wherein a total thickness of the third 2D material layer and the second portion of the second 2D material layer is greater than a thickness of the first 2D material layer;
- and
- a metal contact landing on the third 2D material layer.
A semiconductor device, comprising:
- a substrate having a semiconductor fin;
- a shallow trench isolation (STI) structure over the substrate and laterally surrounding the semiconductor fin;
- a gate structure over the semiconductor fin;
- a plurality of gate spacers on opposite sidewalls of the gate structure;
- a 2D material layer over the substrate, the 2D material layer comprising a first portion and a second portion, wherein the first portion is embedded in the STI structure and in contact with a top surface of the semiconductor fin, a bottom surface of the first portion is lower than a top surface of the STI structure, and the second portion is over the first portion and is in contact with the top surface of the STI structure;
- and
- a source/drain contact in contact with the second portion of the 2D material layer at a position higher than a bottom surface of a gate electrode of the gate structure.
Dependencies are inferred from the claim text.