Method for producing pillar-shaped semiconductor device
AssigneeUnisantis Electronics Singapore Pte. Ltd.
InventorsFujio Masuoka, Nozomu Harada, Yoshiaki Kikuchi
Life of this patent
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Abstract
A SiO2 layer 5 is formed in the bottom portion of a Si pillar 3 and on an i-layer substrate 2. Subsequently, a gate HfO2 layer 11b is formed so as to surround the side surface of the Si pillar 3, and a gate TiN layer 12b is formed so as to surround the HfO2 layer 11b. Subsequently, P+ layers 18 and 32 containing an acceptor impurity at a high concentration and serving as a source and a drain are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar 3. Thus, an SGT is formed on the i-layer substrate 2.
Claims19
A method for producing a pillar-shaped semiconductor device, the method comprising:
- forming a semiconductor pillar so as to stand vertically from a substrate;
- forming a gate insulating layer so as to surround a side surface of the semiconductor pillar;
- forming a gate conductor layer so as to surround a side surface of the gate insulating layer;
- forming a first impurity region below the gate insulating layer in contact with a lower portion or the side surface of the semiconductor pillar, wherein the first impurity region contains a donor or acceptor impurity;
- and
- forming a second impurity region above the gate insulating layer on a top portion of the semiconductor pillar, wherein the second impurity region contains a donor or acceptor impurity,
- wherein the step of forming the second impurity region comprises forming a first material layer around the top portion of the semiconductor pillar, and etching the top portion of the semiconductor pillar using the first material layer as a mask to form a recessed portion above the etched semiconductor pillar,
- the method further comprising:
- forming a second material layer around the side surface of the semiconductor pillar below the gate insulating layer;
- etching the second material layer to form an opening portion around the side surface of the semiconductor pillar below the gate insulating layer;
- and simultaneously forming the second impurity region in the recessed portion and the first impurity region in the opening portion, using a selective epitaxial crystal growth method.
A method for producing a pillar-shaped semiconductor device, the method further comprising:
- forming a semiconductor pillar so as to stand vertically from a substrate;
- forming a gate insulating layer around a side surface of the semiconductor pillar;
- forming a gate conductor layer around a side surface of the gate insulating layer;
- forming a first impurity region below the gate insulating layer in contact with a lower portion or the side surface of the semiconductor pillar, wherein the first impurity region contains a donor or acceptor impurity;
- and
- forming a second impurity region above the gate insulating layer on a top portion of the semiconductor pillar, wherein the second impurity region contains a donor or acceptor impurity,
- wherein the step of forming the first impurity region comprises:
- forming a first material layer around a bottom portion of the semiconductor pillar;
- forming a second material layer on the first material layer around the semiconductor pillar with a constant horizontal width, wherein the second material layer is constituted by a single layer or a plurality of vertically formed layers;
- vertically etching the first material layer, using the second material layer as a mask, to form an opening portion through which a side surface of a lower portion of the semiconductor pillar is exposed;
- and
- forming the first impurity region by a selective epitaxial crystal growth method so that the first impurity region horizontally extends from the side surface of the semiconductor pillar out of the opening portion.
A method for producing a pillar-shaped semiconductor device, the method comprising:
- forming a semiconductor pillar so as to stand vertically from a substrate;
- forming a gate insulating layer so as to surround a side surface of the semiconductor pillar;
- forming a gate conductor layer so as to surround a side surface of the gate insulating layer;
- forming a first impurity region below the gate insulating layer in contact with a lower portion or the side surface of the semiconductor pillar, wherein the first impurity region contains a donor or acceptor impurity;
- and
- forming a second impurity region above the gate insulating layer on a top portion of the semiconductor pillar, wherein the second impurity region contains a donor or acceptor impurity,
- wherein the step of forming the semiconductor pillar comprises etching a semiconductor layer formed on the substrate using, as a mask, a mask material layer formed on the semiconductor layer,
- the step of forming the first impurity region comprises forming a third material layer around the side surface of the semiconductor pillar, and
- the step of forming the second impurity region comprises forming a first material layer around the top portion of the semiconductor pillar and etching the top portion of the semiconductor pillar using the first material layer as a mask to form a recessed portion above the etched semiconductor pillar;
- and
- the method further comprising:
- forming a second material layer around the side surface of the semiconductor pillar below the gate insulating layer;
- etching the second material layer to form an opening portion around the side surface of the semiconductor pillar below the gate insulating layer;
- simultaneously forming the second impurity region in the recessed portion and the first impurity region in the opening portion, using a selective epitaxial crystal growth method;
- and
- performing oxidation, using the mask material layer and the third material layer as anti-oxidation masks, to form an oxidized layer in an upper portion of the semiconductor layer around a bottom portion of the semiconductor pillar.
A method for producing a pillar-shaped semiconductor device, the method further comprising:
- forming a semiconductor pillar so as to stand vertically from a substrate;
- forming a gate insulating layer around a side surface of the semiconductor pillar;
- forming a gate conductor layer around a side surface of the gate insulating layer;
- forming a first impurity region below the gate insulating layer in contact with a lower portion or the side surface of the semiconductor pillar, wherein the first impurity region contains a donor or acceptor impurity;
- and
- forming a second impurity region above the gate insulating layer on a top portion of the semiconductor pillar, wherein the second impurity region contains a donor or acceptor impurity,
- wherein the step of forming the first impurity region comprises:
- forming a first material layer around a bottom portion of the semiconductor pillar;
- forming a second material layer on the first material layer around the semiconductor pillar with a constant horizontal width, wherein the second material layer is constituted by a single layer or a plurality of vertically formed layers;
- vertically etching the first material layer, using the second material layer as a mask, to form an opening portion through which a side surface of a lower portion of the semiconductor pillar is exposed;
- and
- forming the first impurity region by a selective epitaxial crystal growth method so that the first impurity region horizontally extends from the side surface of the semiconductor pillar out of the opening portion,
- wherein the step of forming the semiconductor pillar comprises etching a semiconductor layer formed on the substrate using, as a mask, a mask material layer formed on the semiconductor layer,
- the step of forming the first impurity region comprises forming a third material layer around the side surface of the semiconductor pillar, and
- the method further comprising performing oxidation, using the mask material layer and the third material layer as anti-oxidation masks, to form an oxidized layer in an upper portion of the semiconductor layer around a bottom portion of the semiconductor pillar.
Dependencies are inferred from the claim text.