Vertical fin field effect transistor devices with self-aligned source and drain junctions

A fin field effect transistor device, comprising:

• a vertical fin on a supporting pillar, wherein the supporting pillar is on a substrate;
• a bottom source/drain layer on the substrate adjacent to the supporting pillar;
• a lower doped layer segment on the bottom source/drain layer and a lower section of the vertical fin;
• a bottom spacer layer on the lower doped layer segment;
• an upper doped layer segment on an upper section of the vertical fin;
• and
• a top source/drain on the vertical fin and the upper doped layer segment.

A fin field effect transistor device, comprising:

• a vertical fin on a supporting pillar, wherein the supporting pillar is on a substrate;
• a bottom source/drain layer adjacent to the supporting pillar;
• a lower doped layer segment on the bottom source/drain layer and a lower section of the vertical fin;
• a bottom spacer layer on the doped layer;
• an upper doped layer segment on an upper section of the vertical fin;
• a gate dielectric layer on the bottom spacer layer, lower doped layer segment, sidewalls of the vertical fin, and upper doped layer segment.