Field-effect transistor device with gate spacer structure

A method, comprising:

• providing a workpiece that includes:
• a semiconductor element comprising a channel region and a source/drain region, and
• a dummy gate stack wrapping over the channel region of the semiconductor element;
• depositing a first spacer layer over sidewalls of the dummy gate stack;
• depositing a second spacer layer over the first spacer layer, wherein the second spacer layer comprises at least one silicon sublayer and at least one nitrogen-containing sublayer;
• after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess;
• after the etching, removing the second spacer layer;
• and
• after the removing of the second spacer layer, forming a source/drain feature in the source/drain recess.

A method, comprising:

• forming a dummy gate stack over a semiconductor element;
• depositing a first spacer layer over sidewalls of the dummy gate stack;
• and
• depositing a second spacer layer over the first spacer layer, wherein the depositing of the second spacer layer comprises:
• depositing a silicon sublayer over the first spacer layer using atomic layer deposition (ALD), and
• depositing a nitrogen-containing sublayer over the silicon sublayer using ALD.