Gate structure and patterning method for multiple threshold voltages

A method, comprising:

• providing a workpiece comprising a first, a second, and a third n-type channel regions;
• forming an interfacial layer over the first, second, and third n-type channel regions;
• after the forming of the interfacial layer, selectively forming a first high-k dielectric layer over the interfacial layer over the first n-type channel region, the selectively forming of the first high-k dielectric layer comprising:
• depositing the first high-k dielectric layer over the first n-type channel region, the second n-type channel region, and the third n-type channel region, and
• selectively removing the first high-k dielectric layer over the second n-type channel region and the third n-type channel region;
• after the selectively removing of the first high-k dielectric layer, selectively forming a second high-k dielectric layer over the interfacial layer disposed over the second n-type channel region and over the first high-k dielectric layer disposed over the first n-type channel region;
• depositing a third high-k dielectric layer over the second high-k dielectric layer disposed over the first n-type channel region and the second n-type channel region, and over the interfacial layer disposed over the third n-type channel region;
• forming an n-type work function layer over the third high-k dielectric layer disposed over the first, second, and third n-type channel regions;
• and
• forming a fill metal layer over the n-type work function layer,
• wherein the first, second and third high-k dielectric layers are different from one another.

A method, comprising:

• providing a workpiece comprising a first, a second, and a third p-type channel regions;
• forming an interfacial layer over the first, second, and third p-type channel regions;
• after the forming of the interfacial layer, selectively forming a first high-k dielectric layer over the interfacial layer over the first p-type channel region, the selectively forming of the first high-k dielectric layer comprising:
• depositing the first high-k dielectric layer over the first p-type channel region, the second p-type channel region, and the third p-type channel region, and
• selectively removing the first high-k dielectric layer over the second p-type channel region and the third p-type channel region;
• after the selectively removing of the first high-k dielectric layer, selectively forming a second high-k dielectric layer over the interfacial layer disposed over the second p-type channel region and over the first high-k dielectric layer disposed over the first p-type channel region;
• depositing a third high-k dielectric layer over the second high-k dielectric layer disposed over the first p-type channel region and the second p-type channel region, and over the interfacial layer disposed over the third p-type channel region;
• forming a p-type work function layer over the third high-k dielectric layer disposed over the first, second, and third p-type channel regions;
• forming an n-type work function layer over the p-type work function layer;
• and
• forming a fill metal layer over the n-type work function layer,
• wherein the first, second and third high-k dielectric layers are different from one another.