Select gate spacer formation to facilitate embedding of split gate flash memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Chih-Ren Hsieh
Life of this patent
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Abstract
An integrated circuit device includes a semiconductor substrate having a memory area and a logic area. A memory cell in the memory area includes a select gate separated from a floating gate by a floating gate spacer. A select gate spacer is formed on a side of the select gate opposite the floating gate. The select gate spacer has a uniform thickness over most of the select gate. The first layer of the select gate spacer may be formed by oxidizing the select gate electrode. A second layer of the select gate spacer may be formed by atomic layer deposition. the memory area may be covered by a protective layer while spacers are formed adjacent logic gates in the logic region.
Claims20
An integrated circuit (IC), comprising:
- a semiconductor substrate comprising a memory area and a logic area;
- a plurality of flash memory cells in the memory area, each of the flash memory cells comprising a floating gate, a control gate, and a select gate, each of the select gates comprising a select gate electrode, a select gate dielectric adjacent the semiconductor substrate below the select gate electrode, and a select gate spacer on a side of the select gate electrode opposite the floating gate;
- and
- a plurality of logic gates in the logic area, each of the logic gates comprising a logic gate electrode and logic gate spacers on either side of the logic gate electrode;
- wherein a composition of the select gate spacer is distinct from a composition of the logic gate spacers;
- the select gate spacer comprises a first oxide layer grown from the select gate electrode;
- and
- the select gate spacer has a more vertical profile than the logic gate spacers.
An integrated circuit (IC) comprising:
- a semiconductor substrate comprising a memory area and a logic area;
- a plurality of flash memory cells in the memory area;
- and
- a plurality of logic gates in the logic area;
- wherein each of the flash memory cells comprises a floating gate, a control gate, and a select gate;
- each of the select gates comprises a select gate electrode and a select gate dielectric;
- a select gate spacer disposed adjacent the select gate electrode is an oxidation product of the select gate electrode;
- the oxidation product extends underneath the select gate electrode to provide the select gate dielectric with a variable thickness that is greater adjacent select gate spacer;
- and
- a source/drain region within the semiconductor substrate is doped in alignment with the select gate spacer.
An integrated circuit (IC) comprising:
- a semiconductor substrate comprising a memory area and a logic area;
- a plurality of flash memory cells in the memory area;
- and
- a plurality of logic gates in the logic area;
- wherein each of the flash memory cells comprising a floating gate, a control gate, and a select gate;
- each of the select gates comprises a select gate electrode and a select gate dielectric;
- a select gate spacer structure is disposed adjacent the select gate electrode;
- the select gate spacer structure comprises an oxidation product of the select gate electrode;
- the oxidation product is thicker than a native oxide layer;
- the semiconductor substrate comprises a source-drain region;
- the select gate spacer structure has a sidewall to which the source-drain region is aligned;
- and
- the sidewall is vertical through a height of the select gate electrode.
Dependencies are inferred from the claim text.