Back to results
US 11,380,760 B2Granted
Semiconductor device including a densified device isolation layer
AssigneeSamsung Electronics Co., Ltd.
InventorsKyungin Choi, Hyunchul Song, Sunjung Kim, Taegon Kim, Seong Hoon Jeong
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.
Claims20
A semiconductor device comprising:
- a substrate including a first region and a second region;
- a plurality of fin-shape structures disposed on the substrate, and including a first fin-shape structure, a second fin-shape structure and a third fin-shape structure;
- a plurality of isolation layers disposed on the substrate, and including a first isolation layer and a second isolation layer;
- a first gate electrode disposed on the plurality of fin-shape structures and on the plurality of isolation layers;
- a first gate dielectric pattern disposed between the first gate electrode and the plurality of fin-shape structures, and disposed between the first gate electrode and the plurality of isolation layers;
- a second gate electrode disposed on the plurality of fin-shape structures and on the plurality of isolation layers;
- a second gate dielectric pattern disposed between the second gate electrode and the plurality of fin-shape structures, and disposed between the first gate electrode and the plurality of isolation layers;
- a first source/drain disposed on the first fin-shape structure, and disposed between the first gate electrode and the second gate electrode;
- a second source/drain disposed on the second fin-shape structure, and disposed between the first gate electrode and the second gate electrode;
- and
- a first contact disposed on the first source/drain and on the second source/drain, and disposed between the first gate electrode and the second gate electrode,
- wherein the first fin-shape structure is disposed on the first region of the substrate,
- the second fin-shape structure and the third fin-shape structure are disposed on the second region of the substrate,
- the first isolation layer is disposed between the first fin-shape structure and the second fin-shape structure,
- a second isolation layer is disposed between the second fin-shape structure and the third fin-shape structure,
- a width of the first isolation layer is greater than a width of the second isolation layer,
- a depth of the first isolation layer is greater than a depth of the second isolation layer, and
- an upper surface of the second isolation layer is disposed higher than an upper surface of the first isolation layer.
15 more elements
A semiconductor device comprising:
- a substrate including a first region and a second region;
- a plurality of fin-shape structures disposed on the substrate, and including a first fin-shape structure, a second fin-shape structure and a third fin-shape structure;
- a plurality of isolation layers disposed on the substrate, and including a first isolation layer and a second isolation layer;
- a first gate dielectric pattern disposed on the plurality of fin-shape structures and on the plurality of isolation layers;
- a first gate electrode disposed on the first gate dielectric pattern;
- a second gate dielectric pattern disposed on the plurality of fin-shape structures and on the plurality of isolation layers;
- a second gate electrode disposed on the second gate dielectric pattern;
- a first source/drain disposed on the first fin-shape structure, and disposed between the first gate electrode and the second gate electrode;
- a second source/drain disposed on the second fin-shape structure, and disposed between the first gate electrode and the second gate electrode;
- and
- a first contact disposed on the first source/drain and on the second source/drain, and disposed between the first gate electrode and the second gate electrode,
- wherein the first fin-shape structure is disposed on the first region of the substrate,
- the second fin-shape structure and the third fin-shape structure are disposed on the second region of the substrate,
- the first isolation layer is disposed between the first fin-shape structure and the second fin-shape structure,
- a second isolation layer is disposed between the second fin-shape structure and the third fin-shape structure,
- a width of the first isolation layer is greater than a width of the second isolation layer,
- a depth of the first isolation layer is greater than a depth of the second isolation layer,
- the first gate dielectric pattern includes a first portion disposed on the first isolation layer and a second portion disposed on the second isolation layer, and
- a bottom surface of the second portion of the first gate dielectric pattern is disposed higher than a bottom surface of the first portion of the first gate dielectric pattern.
16 more elements
A semiconductor device comprising:
- a substrate including a first region and a second region;
- a plurality of fin-shape structures disposed on the substrate, and including a first fin-shape structure, a second fin-shape structure and a third fin-shape structure;
- a plurality of isolation layers disposed on the substrate, and including a first isolation layer and a second isolation layer;
- a first gate dielectric pattern disposed on the plurality of fin-shape structures and on the plurality of isolation layers;
- a first gate electrode disposed on the first gate dielectric pattern;
- a second gate dielectric pattern disposed on the plurality of fin-shape structures and on the plurality of isolation layers;
- a second gate electrode disposed on the second gate dielectric pattern;
- a first source/drain disposed on the first fin-shape structure, and disposed between the first gate electrode and the second gate electrode;
- a second source/drain disposed on the second fin-shape structure, and disposed between the first gate electrode and the second gate electrode;
- and
- a first contact disposed on the first source/drain and on the second source/drain, and disposed between the first gate electrode and the second gate electrode,
- wherein the first fin-shape structure is disposed on the first region of the substrate,
- the second fin-shape structure and the third fin-shape structure are disposed on the second region of the substrate,
- the first isolation layer is disposed between the first fin-shape structure and the second fin-shape structure,
- a second isolation layer is disposed between the second fin-shape structure and the third fin-shape structure,
- a width of the first isolation layer is greater than a width of the second isolation layer,
- a depth of the first isolation layer is greater than a depth of the second isolation layer,
- the first gate electrode includes a first portion disposed on the first isolation layer and a second portion disposed on the second isolation layer, and
- a bottom surface of the second portion of the first gate electrode is disposed higher than a bottom surface of the first portion of the first gate electrode.
16 more elements
Dependencies are inferred from the claim text.