Memory with optimized resistive layers

A memory device, comprising:

• a substrate;
• a plurality of memory stacks positioned on the substrate, each memory stack comprising a layered assembly of electrode materials and memory material;
• a via positioned on the substrate, the via comprising a conductive material;
• a first resistive material positioned on the plurality of memory stacks, wherein the first resistive material covers the plurality of memory stacks and fails to cover the via;
• a first conductive material positioned on the plurality of memory stacks over the first resistive material;
• a second resistive material positioned on the first conductive material and the via;
• and
• a second conductive material positioned on the second resistive material.

A memory device, comprising:

• a substrate;
• a plurality of memory stacks positioned on the substrate, each memory stack comprising a layered assembly of electrode materials and memory material;
• a via positioned on the substrate, the via comprising a conductive material;
• a first resistive material positioned on the plurality of memory stacks, wherein the first resistive material covers the plurality of memory stacks and fails to cover the via;
• a first conductive material positioned on the plurality of memory stacks over the first resistive material;
• a second resistive material positioned on the first conductive material and the via, wherein the conductive material of the via is in direct contact with the second resistive material;
• and
• a second conductive material positioned on the second resistive material.

A memory device, comprising:

• a plurality of first access lines extending in a first direction;
• respective pluralities of memory stacks on the plurality of first access lines;
• a plurality of vias, each aligned in a second direction with a group of memory stacks, each group of memory stacks comprising a memory stack from each of the plurality of first access lines that are aligned in the second direction with the via, each via comprising a conductive material;
• and
• a plurality of second access lines extending in the second direction, each second access line extending over a via of the plurality of vias and the group of memory stacks aligned with the via,
• wherein each second access line comprises:
• a first resistive material positioned directly on each memory stack of the respective pluralities of memory stacks;
• a first conductive material positioned on the first resistive material;
• a second resistive material positioned on the via and the first conductive material;
• and
• a second conductive material positioned on the second resistive material.

A memory device, comprising:

• a plurality of first access lines extending in a first direction;
• respective pluralities of memory stacks on the plurality of first access lines;
• a plurality of vias, each aligned in a second direction with a group of memory stacks, each group of memory stacks comprising a memory stack from each of the plurality of first access lines that are aligned in the second direction with the via, each via comprising a conductive material;
• and
• a plurality of second access lines extending in the second direction, each second access line extending over a via of the plurality of vias and the group of memory stacks aligned with the via,
• wherein each second access line comprises:
• a first resistive material positioned on each memory stack of the respective pluralities of memory stacks;
• a first conductive material positioned on the first resistive material;
• a second resistive material positioned on the via and the first conductive material, wherein the conductive material of each via is in direct contact with the second resistive material;
• and
• a second conductive material positioned on the second resistive material.