Sensor device
AssigneeSamsung Electronics Co., Ltd.
InventorHyunsu Jun
Life of this patent
Estimating the term…
Abstract
A sensor device including an interposer including a first via and a lower pad, the lower pad being on a bottom surface of the interposer; an image sensor chip on a top surface of the interposer, the image sensor chip including a logic chip and a sensing chip on the logic chip, the logic chip including first wiring patterns and a second via, and the sensing chip including second wiring patterns; a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure being connected to at least one of the first wiring patterns and at least one of the second wiring patterns; and a passivation layer on an inner surface of the conductive structure, wherein a side surface of the interposer is coplanar with a side surface of the image sensor chip.
Claims20
A sensor device, comprising:
- an interposer including a first via and a lower pad, the lower pad being on a bottom surface of the interposer;
- an image sensor chip on a top surface of the interposer, the image sensor chip including a logic chip and a sensing chip on the logic chip, the logic chip including first wiring patterns and a second via, and the sensing chip including second wiring patterns;
- a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure being connected to at least one of the first wiring patterns and at least one of the second wiring patterns;
- and
- a passivation layer on an inner surface of the conductive structure,
- wherein a side surface of the interposer is coplanar with a side surface of the image sensor chip.
A sensor device, comprising:
- an interposer including a lower pad and a first via connected to the lower pad, the lower pad being on a bottom surface of the interposer;
- a re-distribution layer on a top surface of the interposer, the re-distribution layer including redistribution patterns;
- an image sensor chip stacked on a top surface of the re-distribution layer, the image sensor chip including a logic chip and a sensing chip stacked on the logic chip, the logic chip including a first circuit layer, and the sensing chip including a second circuit layer;
- a conductive structure penetrating a portion of the logic chip and the sensing chip and having a recess;
- and
- a passivation layer in the recess and covering an inner surface of the conductive structure,
- wherein:
- the first circuit layer includes first wiring patterns and the second circuit layer includes second wiring patterns,
- the conductive structure is in direct contact with at least one of the first wiring patterns in the first circuit layer and is in direct contact with at least one of the second wiring patterns in the second circuit layer, and
- a side surface of the interposer is vertically aligned to a side surface of the image sensor chip.
A sensor device, comprising:
- an interposer including a lower pad and a first via connected to the lower pad, the lower pad being on a bottom surface of the interposer, and the first via extending in a first direction;
- a re-distribution layer on a top surface of the interposer, the re-distribution layer including redistribution patterns;
- an image sensor chip stacked on a top surface of the re-distribution layer, the image sensor chip including a logic chip and a sensing chip stacked on the logic chip, the logic chip including a first circuit layer and a second via, and the sensing chip including a second circuit layer;
- color filters and micro lenses on a top surface of the image sensor chip;
- a conductive structure penetrating a portion of the logic chip and the sensing chip and having a recess;
- and
- a passivation layer in the recess and covering an inner surface of the conductive structure,
- wherein:
- the first circuit layer includes first wiring patterns and the second circuit layer includes second wiring patterns,
- the conductive structure is in direct contact with at least one of the first wiring patterns in the first circuit layer and at least one of the second wiring patterns in the second circuit layer,
- a first connection pad in an upper portion of the first circuit layer is electrically connected to a second connection pad in a lower portion of the second circuit layer,
- the first via is electrically connected to the redistribution patterns,
- the second via is electrically connected to the first wiring patterns and the redistribution patterns, and
- a side surface of the interposer is vertically aligned to a side surface of the image sensor chip.
Dependencies are inferred from the claim text.