Array substrate, display panel and display device

A display panel, comprising an array substrate, wherein the array substrate comprises:

• a plurality of gate lines and a plurality of data lines,
• wherein the plurality of gate lines and the plurality of data lines define rows of sub-pixel regions, each of the sub-pixel regions comprise two thin film transistors and a pixel electrode, and the two thin film transistors are both connected with the pixel electrode;
• gate electrodes of two thin film transistors in a sub-pixel region in an (n)th row of the rows of sub-pixel regions are respectively connected with an (n)th gate line and an (n+1)th gate line of the plurality of gate lines, K≥n≥1, n and K are integers, and K is an amount of rows of the sub-pixel regions;
• and
• a drive circuit;
• wherein the drive circuit comprises K+2 gate drive circuits arranged in cascade, a first gate drive circuit of the K+2 gate drive circuits is connected with a first gate line of the plurality of gate lines, a last gate drive circuit of the K+2 gate drive circuits is connected with a last gate line of the plurality of gate lines, a (s)th gate drive circuit of the K+2 gate drive circuits is simultaneously connected with a (s−1)th gate line and a (s)th gate line of the plurality of gate lines, and K+1≥s≥2.

A display device, comprising a display panel, wherein the display panel comprises:

• an array substrate, wherein the array substrate comprises:
• a plurality of gate lines and a plurality of data lines,
• wherein the plurality of gate lines and the plurality of data lines define rows of sub-pixel regions, each of the sub-pixel regions comprise two thin film transistors and a pixel electrode, and the two thin film transistors are both connected with the pixel electrode;
• gate electrodes of two thin film transistors in a sub-pixel region in an (n)th row of the rows of sub-pixel regions are respectively connected with an (n)th gate line and an (n+1)th gate line of the plurality of gate lines, K≥n≥1, n and K are integers, and K is an amount of rows of the sub-pixel regions;
• and
• a drive circuit;
• wherein the drive circuit comprises K+2 gate drive circuits arranged in cascade, a first gate drive circuit of the K+2 gate drive circuits is connected with a first gate line of the plurality of gate lines, a last gate drive circuit of the K+2 gate drive circuits is connected with a last gate line of the plurality of gate lines, a (s)th gate drive circuit of the K+2 gate drive circuits is simultaneously connected with a (s−1)th gate line and a (s)th gate line of the plurality of gate lines, and K+1≥s≥2.