Array substrate and manufacturing method thereof, display panel

A manufacturing method of an array substrate, comprising:

• forming a first conductive layer on a base substrate, wherein the first conductive layer comprises a first signal line;
• forming a first insulating layer on the first conductive layer and a first via hole in the first insulating layer;
• forming a second conductive layer on the first insulating layer, wherein the second conductive layer comprises a second signal line and a first connection part which are spaced apart from each other, and the first connection part is electrically connected with the first signal line through the first via hole;
• an orthographic projection of the second signal line on the base substrate is intersected with an orthographic projection of the first signal line on the base substrate;
• and the first connection part is in contact with an upper surface of the first insulating layer;
• and
• forming a third conductive layer on the second conductive layer, wherein the third conductive layer comprises a second connection part, and the second connection part is electrically connected with the first connection part and the second signal line, respectively, to constitute a connection structure electrically connect the first signal line with the second signal line,
• wherein the first conductive layer comprises a plurality of first signal lines extended in a first direction, and the second conductive layer comprises a plurality of second signal lines extended in a second direction;
• wherein the plurality of first signal lines and the plurality of second signal lines overlap each other at overlap positions respectively, in the direction perpendicular to the base substrate, and the connection structure is provided at each of the overlap positions;
• the second direction intersects the first direction;
• the array substrate further comprises a plurality of sub-pixels arranged in a plurality of rows along the first direction and a plurality of columns along the second direction;
• each sub-pixel comprises a thin film transistor, and the first signal line and the second signal line are electrically connected with a source electrode or a drain electrode of the thin film transistor;
• and
• each sub-pixel further comprises a pixel electrode, and the third conductive layer further comprises the pixel electrode.