Back to results
US 11,380,709 B2Granted
Three dimensional ferroelectric memory
AssigneeSanDisk Technologies LLC
InventorsYingda Dong, James Kai, Christopher J. Petti
Life of this patent
Estimating the term…
Abstract
A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.
Claims20
A memory element comprising:
- a portion of a bit line plug;
- a portion of a source line plug;
- a portion of a word line;
- a portion of a vertical semiconductor pillar disposed between the portion of the bit line plug, the portion of the source line plug and adjacent the portion of the word line;
- and
- a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line,
- wherein:
- the bit line plug has a long axis that extends substantially an entire length of a long axis of the vertical semiconductor pillar;
- and
- the source line plug has a long axis that extends substantially the entire length of the long axis of the vertical semiconductor pillar.
7 more elements
A memory array comprising:
- a plurality of bit line plugs disposed in parallel along a first axis;
- a plurality of source line plugs disposed in parallel along the first axis;
- a plurality of word lines disposed in parallel substantially perpendicular to the first axis;
- a plurality of vertical semiconductor pillars;
- and
- a plurality of memory elements, each memory element comprising a portion of a corresponding bit line plug, a portion of a corresponding source line plug, a portion of a corresponding word line, a portion of a corresponding vertical semiconductor pillar disposed between the portion of the corresponding bit line plug, the portion of the corresponding source line plug and adjacent the portion of the corresponding word line, and a gate oxide including a ferroelectric material disposed between each of the vertical semiconductor pillars and each adjacent word line,
- wherein:
- each bit line plug has a long axis that extends substantially an entire length of a long axis of the vertical semiconductor pillars;
- and
- each source line plug has a long axis that extends substantially the entire length of the long axis of the vertical semiconductor pillars.
7 more elements
A three-dimensional memory array comprising:
- a first memory level disposed above a substrate, the first memory level comprising a first ferroelectric field-effect transistor comprising a first portion of a bit line plug, a first portion of a source line plug, a portion of a first word line, a first portion of a vertical semiconductor pillar disposed between the first portion of the bit line plug, the first portion of the source line plug and adjacent the portion of the first word line, and a first gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the first word line;
- and
- a second memory level disposed above the first memory level, the second memory level comprising a second ferroelectric field-effect transistor comprising a second portion of the bit line plug, a second portion of the source line plug, a portion of a second word line, a second portion of the vertical semiconductor pillar disposed between the second portion of the bit line plug, the second portion of the source line plug and adjacent the portion of the second word line, and a second gate oxide including the ferroelectric material disposed between the vertical semiconductor pillar and the second word line.
Dependencies are inferred from the claim text.