Integrated circuit device and method of manufacturing the same

An integrated circuit device comprising:

• a first stacked structure comprising a plurality of first conductive lines extending in a first direction in parallel with a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate;
• a second stacked structure comprising a plurality of second conductive lines extending in the first direction in parallel with the main surface of the substrate and overlapping one another in the vertical direction vertical to the main surface, on the first stacked structure;
• a channel layer extending in the vertical direction in a channel hole passing through the first and second stacked structures;
• and
• a plurality of outer blocking dielectric layers between the plurality of first and second conductive lines and the channel layer, in all of the plurality of first conductive lines and at least some of the plurality of second conductive lines,
• wherein a width of each of the plurality of outer blocking dielectric layers in a horizontal direction increases toward the main surface.

An integrated circuit device comprising:

• a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate;
• a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction;
• a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers;
• a charge storage layer and a first blocking dielectric layer each extending in an extension direction of the channel layer between the plurality of conductive lines and the channel layer, in the channel hole;
• and
• a plurality of second blocking dielectric layers between the plurality of conductive lines and the first blocking dielectric layer and between the plurality of conductive lines and the plurality of insulation layers, in at least some of the plurality of conductive lines,
• wherein, with respect to the channel hole, a first width of a second blocking dielectric layer of an uppermost conductive line among the plurality of conductive lines operating as a memory cell is set in the horizontal direction,
• a second width of a second blocking dielectric layer of a lowermost conductive line among the plurality of conductive lines operating as a memory cell is set in the horizontal direction,
• a third width of a second blocking dielectric layer of a center conductive line closest to the uppermost conductive line and the lowermost conductive line in the vertical direction is set in the horizontal direction,
• the third width is greater than the first width, and
• the second width is greater than the third width.