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US 11,380,704 B2Granted
Semiconductor memory device and method of manufacturing semiconductor memory device
AssigneeKioxia Corporation
InventorTomoya Inden
Life of this patent
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Abstract
A semiconductor memory device includes a P-type transistor and a first N-type transistor. The P-type transistor includes a first semiconductor layer containing carbon, a P-type second semiconductor layer provided on the first semiconductor layer, a third semiconductor layer provided on the second semiconductor layer and containing carbon. The first N-type transistor includes a fourth semiconductor layer containing carbon, an N-type fifth semiconductor layer provided on the fourth semiconductor layer, a sixth semiconductor layer provided on the fifth semiconductor layer and containing carbon.
Claims9
A semiconductor memory device comprising:
- a memory cell;
- and
- a P-type transistor, a first N-type transistor, a second N-type transistor, and a third N-type transistor provided on a top surface of a substrate and electrically coupled to the memory cell,
- the P-type transistor including:
- a first gate insulating layer provided on the substrate;
- a first source region provided in the substrate;
- a first drain region provided in the substrate;
- and
- a first gate electrode provided on the first gate insulating layer,
- the first gate electrode including:
- a first semiconductor layer containing carbon;
- a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer being a P-type;
- a third semiconductor layer provided on the second semiconductor layer;
- and
- a first conductive layer provided above the third semiconductor layer,
- the first N-type transistor including:
- a second gate insulating layer provided on the substrate;
- a second source region provided in the substrate;
- a second drain region provided in the substrate;
- and
- a second gate electrode provided on the second gate insulating layer,
- the second gate electrode including:
- a fourth semiconductor layer containing carbon;
- a fifth semiconductor layer provided on the fourth semiconductor layer, the fifth semiconductor layer being an N-type;
- a sixth semiconductor layer provided on the fifth semiconductor layer and containing carbon;
- and
- a second conductive layer provided above the sixth semiconductor layer,
- the second N-type transistor including:
- a third gate insulating layer provided on the substrate;
- a seventh semiconductor layer provided above the third gate insulating layer and containing carbon;
- an eighth semiconductor layer provided on the seventh semiconductor layer, the eighth semiconductor layer being the N-type;
- and
- a ninth semiconductor layer provided on the eighth semiconductor layer and containing carbon,
- the third N-type transistor including:
- a fourth gate insulating layer provided on the substrate;
- a tenth semiconductor layer provided above the fourth gate insulating layer and containing carbon;
- an eleventh semiconductor layer provided on the tenth semiconductor layer, the eleventh semiconductor layer being the N-type;
- and
- a twelfth semiconductor layer provided on the eleventh semiconductor layer and containing carbon,
- the fourth gate insulating layer being thicker than the third gate insulating layer, and
- the third gate insulating layer being thicker than the first gate insulating layer and the second gate insulating layer.
38 more elements
A semiconductor memory device comprising:
- a memory cell;
- and
- a P-type transistor, a first N-type transistor, a second N-type transistor, and a third N-type transistor provided on a top surface of a substrate and electrically coupled to the memory cell,
- the P-type transistor including:
- a first gate insulating layer provided on the substrate;
- a first source region provided in the substrate;
- a first drain region provided in the substrate;
- and
- a first gate electrode provided on the first gate insulating layer,
- the first gate electrode including:
- a first semiconductor layer containing carbon;
- a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer being a P-type;
- a third semiconductor layer provided on the second semiconductor layer;
- a first insulating layer provided on the third semiconductor layer;
- and
- a first conductive layer provided on the first insulating layer,
- the first N-type transistor including:
- a second gate insulating layer provided on the substrate;
- a second source region provided in the substrate;
- a second drain region provided in the substrate;
- and
- a second gate electrode provided on the second gate insulating layer,
- the second gate electrode including:
- a fourth semiconductor layer containing carbon;
- a fifth semiconductor layer provided on the fourth semiconductor layer, the fifth semiconductor layer being an N-type;
- a second insulating layer provided on the fifth semiconductor layer;
- and
- a second conductive layer provided on the second insulating layer,
- the second N-type transistor including:
- a third gate insulating layer provided on the substrate;
- a sixth semiconductor layer provided above the third gate insulating layer and containing carbon;
- a seventh semiconductor layer provided on e sixth semiconductor layer, the seventh semiconductor layer being an N-type;
- and
- the third N-type transistor including:
- a fourth gate insulating layer provided on the substrate;
- an eighth semiconductor layer provided above the fourth gate insulating layer and containing carbon;
- and
- a ninth semiconductor layer provided on the eighth semiconductor layer, the ninth semiconductor layer being the N-type,
- the fourth gate insulating layer being thicker than the third gate insulating layer, and
- the third gate insulating layer being thicker than the first gate insulating layer and the second gate insulating layer.
37 more elements
Dependencies are inferred from the claim text.