Memory cell arrangement and method thereof
AssigneeFerroelectric Memory GmbH
InventorJohannes Ocker
Life of this patent
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Abstract
A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.
Claims20
Memory cell arrangement, comprising:
- one or more memory cells, each of the one or more memory cells comprising:
- an electrode pillar having a bottom surface and a top surface;
- a memory material portion surrounding a lateral surface portion of the electrode pillar;
- an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure;
- and
- a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.
Memory cell arrangement, comprising:
- one or more memory cells, each of the one or more memory cells comprising:
- an electrode pillar extending from a bottom surface of the electrode pillar to a top surface of the electrode pillar;
- one or more memory material portions, each of the one or more memory material portions surrounding a respective first lateral surface portion of the electrode pillar;
- one or more first electrode layers, each of the one or more first electrode layers surrounding a corresponding memory material portion of the one or more memory material portions and the first lateral surface portion of the electrode pillar associated with the corresponding memory material portion;
- wherein each of the first electrode layers, the corresponding memory material portion, and the electrode pillar form a respective capacitive memory structure;
- a dielectric material portion surrounding a second lateral surface portion of the electrode pillar different from each of the first lateral surface portions;
- a second electrode layer surrounding the dielectric material portion and the second lateral surface portion of the electrode pillar, wherein the electrode pillar, the dielectric material portion, and the second electrode layer form a capacitive lever structure;
- and
- a field-effect transistor structure comprising a gate structure, wherein the gate structure faces the bottom surface of the electrode pillar and is electrically conductively connected to the electrode pillar.
Method for manufacturing a memory cell arrangement, the method comprising:
- forming one or more field-effect transistor structures;
- forming an electrode layer stack above the one or more field-effect transistor structures, wherein the electrode layer stack comprises at least a first electrode layer, a second electrode layer, and an electrically isolating interlayer disposed between the first electrode layer and the second electrode layer;
- forming one or more recesses into the electrode layer stack, each of the one or more recesses corresponding to one of the one or more field-effect transistor structures, wherein the one or more recesses extend at least through the first electrode layer, the electrically isolating interlayer, and the second electrode layer;
- partially filling the one or more recesses with a memory material, the memory material at least covering a sidewall of each of the one or more recesses;
- and, subsequently;
- at least partially filling a remaining space in each of the one or more recesses with an electrode material, wherein, in each of the one or more recesses, a portion of the memory material is disposed between a portion of the electrode material and at least one of the first electrode layer and/or the second electrode layer, wherein the electrode material in each of the one or more recesses is electrically conductively connected to a gate of a field-effect transistor structure of the one or more field-effect transistor structures corresponding to the recess.
Dependencies are inferred from the claim text.