US 11,380,693 B2Granted

Semiconductor device including anti-fuse cell structure

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsMeng-Sheng Chang, Yao-Jen Yang

Life of this patent

Estimating the term…

Loading patent…

Abstract

A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

Claims20

Dependent claims

A device comprising:

a first active region including a semiconductor material and extending in a first direction;
a first pair of transistors, on the first active region, including a first pair of gates crossing over the first active region, a first source/drain region, and a second source/drain region, wherein the first pair of gates are arranged between the first source/drain region and the second source/drain region;
a second pair of transistors, on the first active region, including a second pair of gates crossing over the first active region, a third source/drain region, and a fourth source/drain region, wherein the second pair of gates are arranged between the third source/drain region and the fourth source/drain region;
at least one dummy transistor, on the first active region, including at least one dummy gate crossing over the first active region and arranged between the first pair of gates and the second pair of gates, the at least one dummy transistor corresponding to at least one non-functional transistor;
a first bit line, over the first active region, extending in the first direction, wherein the first bit line is electrically coupled to the first source/drain region and the third source/drain region;
and
a first via positioned between the third source/drain region and the first bit line, the first via electrically coupling the third source/drain region and the first bit line together.

4 more elements

A device comprising:

a first active region extending in a first direction;
a first pair of transistors including a first pair of gates overlapping the first active region and extending in a second direction different from the first direction, a first source/drain region in the first active region, and a second source/drain region in the first active region, wherein the first pair of gates are between the first source/drain region and the second source/drain region;
a second pair of transistors including a second pair of gates overlapping the first active region and extending in the second direction, a third source/drain region in the first active region, and a fourth source/drain region in the first active region, wherein the second pair of gates are between the third source/drain region and the fourth source/drain region;
a first dummy transistor including a first dummy gate overlapping the first active region, extending in the second direction, and being between the first pair of gates and the second pair of gates, the first dummy transistor corresponding to a first non-functional transistor;
a first bit line extending in the first direction and overlapping the first active region, wherein the first bit line is electrically coupled to the first source/drain region and the third source/drain region;
and
a first via positioned between the third source/drain region and the first bit line, the first via electrically coupling the third source/drain region and the first bit line together.

4 more elements

A device comprising:

a first active region extending in a first direction and including a semiconductor material;
a first pair of transistors including a first pair of gates overlapping the first active region and extending in a second direction different from the first direction, a first source/drain region in the first active region, and a second source/drain region in the first active region, wherein the first pair of gates are between the first source/drain region and the second source/drain region;
a second pair of transistors including a second pair of gates overlapping the first active region and extending in the second direction, a third source/drain region in the first active region, and a fourth source/drain region in the first active region, wherein the second pair of gates are between the third source/drain region and the fourth source/drain region;
a first dummy transistor including a first dummy gate overlapping the first active region, extending in the second direction, and being between the first pair of gates and the second pair of gates, the first dummy transistor corresponding to a first non-functional transistor;
a first bit line extending in the first direction, overlapping the first active region, being on a first metal layer, and being electrically coupled to the first source/drain region and the third source/drain region;
a first via positioned between the third source/drain region and the first bit line, the first via electrically coupling the third source/drain region and the first bit line together;
and
a first word line extending in the second direction, overlapping the first active region, being electrically coupled to a first gate of the first pair of gates, and being on a second metal layer above the first metal layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/533,359Filed 6 Aug 2019 · us provisional application
Priority: 20 Aug 2018
Published: US 2020/0058660 A120 Feb 2020
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/43
Characterised by their conductive parts: layouts of interconnections
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G11C 17/16
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
G11C 17/18
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…