Semiconductor devices including work function layers

A semiconductor device comprising:

• a substrate;
• a first transistor on the substrate, the first transistor having a first threshold voltage,
• the first transistor including a first N-type active region having a plurality of first N-type active patterns vertically aligned on the substrate, a first gate electrode extending across the first N-type active region, and a first gate dielectric layer between the first N-type active region and the first gate electrode,
• the first gate electrode having a first work function layer,
• the first gate dielectric layer having high-k dielectrics containing La,
• the first work function layer including a first layer on the first gate dielectric layer and having TiON, a second layer on the first layer and having TiN or TiON, a third layer on the second layer and having TiON, a fourth layer on the third layer and having TiN, and a fifth layer on the fourth layer and having TiAlC;
• and
• a second transistor on the substrate, the second transistor having a second threshold voltage different from the first threshold voltage,
• the second transistor including a first P-type active region having a plurality of first P-type active patterns vertically aligned on the substrate, a second gate electrode extending across the first P-type active region, and a second gate dielectric layer between the first P-type active region and the second gate electrode,
• the second gate electrode having a second work function layer,
• the second gate dielectric layer having high-k dielectrics, and
• the second work function layer including the fifth layer directly contacting the second gate dielectric layer.

A semiconductor device comprising:

• a substrate;
• first to third N-type active regions and first to third P-type active regions on the substrate, the first to third N-type active regions and the first to third P-type active regions being spaced apart from one another;
• a first gate electrode extending across the first N-type active region, the first gate electrode having a first work function layer;
• a second gate electrode extending across the first P-type active region, the second gate electrode having a second work function layer;
• a third gate electrode extending across the second N-type active region, the third gate electrode having a third work function layer;
• a fourth gate electrode extending across the third N-type active region, the fourth gate electrode having a fourth work function layer;
• a fifth gate electrode extending across the second P-type active region, the fifth gate electrode having a fifth work function layer;
• a sixth gate electrode extending across the third P-type active region, the sixth gate electrode having a sixth work function layer;
• a first gate dielectric layer between the first N-type active region and the first gate electrode, the first gate dielectric layer between the third N-type active region and the fourth gate electrode, the first gate dielectric layer between the second P-type active region and the fifth gate electrode, and the first gate dielectric layer between the third P-type active region and the sixth gate electrode,
• the first gate dielectric layer having high-k dielectrics containing La;
• and
• a second gate dielectric layer between the first P-type active region and the second gate electrode, the second gate dielectric layer between the second N-type active region and the third gate electrode, the second gate dielectric layer having high-k dielectrics;
• a first layer, a second layer, a third layer, a fourth layer, and a fifth layer on the substrate,
• the first layer including TiON,
• the second layer including TiN or TiON,
• the third layer including TiON,
• the fourth layer including TiN,
• the fifth layer including TiAlC,
• the first work function layer including the first layer on the first gate dielectric layer, the second layer on the first layer, the third layer on the second layer, the fourth layer on the third layer, and the fifth layer on the fourth layer,
• the second work function layer including the fifth layer directly contacting the second gate dielectric layer,
• the third work function layer including the first layer on the second gate dielectric layer, the second layer on the first layer, the third layer on the second layer, the fourth layer on the third layer, and the fifth layer on the fourth layer,
• the fourth work function layer including the third layer on the first gate dielectric layer, the fourth layer on the third layer, and the fifth layer on the fourth layer,
• the fifth work function layer including the fourth layer on the first gate dielectric layer and the fifth layer on the fourth layer, and
• the sixth work function layer including the fifth layer directly contacting the first gate dielectric layer.