US 11,380,684 B2Granted

Stacked transistor architecture including nanowire or nanoribbon thin film transistors

AssigneeIntel Corporation

InventorsGilbert Dewey, Aaron Lilak, Cheng-Ying Huang, Jack Kavalieros, Willy Rachmady, Anh Phan, Ehren Mannebach, Abhishek Sharma, Patrick Morrow, Hui Jae Yoo

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Abstract

Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

Claims24

Dependent claims

An integrated circuit structure, comprising:

a first transistor structure including a first nanowire or nanoribbon extending between a first source region and a first drain region, a first gate electrode wrapped around the first nanowire or nanoribbon, and a first gate dielectric between the first nanowire or nanoribbon and the first gate electrode;
and
a second transistor structure above the first transistor structure and arranged in a stacked configuration with the first transistor structure, the second transistor structure including a second nanowire or nanoribbon extending between a second source region and a second drain region, a second gate electrode wrapped around the second nanowire or nanoribbon, and a second gate dielectric between the second nanowire or nanoribbon and the second gate electrode, wherein one of the first or second nanowire or nanoribbon includes a semiconducting oxide material, and wherein the second nanowire or nanoribbon is compositionally different from the first nanowire or nanoribbon.

An integrated circuit structure, comprising:

a first transistor structure including a first nanowire or nanoribbon extending between a first source region and a first drain region, and including a first semiconducting oxide;
a first gate electrode wrapped around the first nanowire or nanoribbon;
and
a first gate dielectric between the first nanowire or nanoribbon and the first gate electrode, and including a high-k dielectric material;
and
a second transistor structure above the first transistor structure and arranged in a stacked configuration with the first transistor structure, the second transistor structure including a second nanowire or nanoribbon extending between a second source region and a second drain region, and including a second semiconducting oxide, wherein the second nanowire or nanoribbon is compositionally different from the first nanowire or nanoribbon;
a second gate electrode wrapped around the second nanowire or nanoribbon;
and
a second gate dielectric between the second nanowire or nanoribbon and the second gate electrode, and including a high-k dielectric material.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/145,817Filed 28 Sep 2018
Published: US 2020/0105751 A12 Apr 2020
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 84/856
Complementary IGFETs, e.g. CMOS: the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
H10D 88/00
Three-dimensional [3d] integrated devices
B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels