FET capacitor circuit architectures for tunable load and input matching

An integrated circuit (IC) with tunable capacitance, comprising:

• a first circuit node to convey a radio frequency (RF) signal, the first circuit node coupled in electrical parallel to gate electrodes of a plurality of Group III-nitride (III-N) field effect transistor (FET) capacitor structures, wherein individual ones of the III-N FET capacitor structures further comprise:
• a source and drain coupled through a III-N material;
• and
• a gate electrode between the source and the drain, wherein a first of the FET capacitor structures comprises a first gate electrode separated from the III-N material by a first distance and a second of the FET capacitor structures comprises a second gate electrode separated from the III-N material by a second distance, different than the first distance;
• a second circuit node to convey the RF signal, the second circuit node coupled to at least one of a source and a drain of individual ones of the III-N FET capacitor structures, wherein:
• a threshold voltage of the III-N FET capacitor structures varies across the plurality;
• and
• the tunable capacitance is to vary with a number of the III-N FET capacitor structures that are in an on-state as a function of a bias voltage between the first and second circuit nodes relative to the threshold voltage of individual ones of the III-N FET capacitor structures.

A method of forming an integrated circuit (IC), the method comprising:

• receiving a workpiece comprising a first III-N material under a second III-N material;
• forming a first FET capacitor structure within a first region of the workpiece, wherein the first FET capacitor structure has a first source-gate threshold voltage;
• forming a second FET capacitor structure within a second region of the workpiece, wherein the second FET capacitor structure has a second source-gate threshold voltage, different than the first source-gate threshold voltage;
• coupling both a source and a drain of the first FET capacitor structure in electrical parallel with a source and a drain of the second FET capacitor structure;
• and
• coupling a gate electrode of the first FET capacitor structure in electrical parallel with a gate electrode of the second FET capacitor structure.