Back to results
US 11,380,667 B2Granted
Memory device with a multiplexed command/address bus
AssigneeMicron Technology, Inc.
InventorWilliam A. Lendvay
Life of this patent
Estimating the term…
Abstract
A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command/address signals from one of the RCD and the controller to the first plurality of volatile memories.
Claims21
An apparatus, comprising:
- a plurality of volatile memories;
- a non-volatile memory;
- a controller coupled to the non-volatile memory;
- a registering clock driver (RCD);
- a command/address (C/A) multiplexer including a first C/A mux input coupled to an output of the RCD, a second C/A mux input coupled to the controller, and a C/A mux output coupled to the plurality of volatile memories;
- and
- a data multiplexer including a first data mux input coupled to an external connector of the apparatus, a second data mux input coupled to the controller, and a data mux output coupled to at least one of the plurality of volatile memories,
- wherein the output of the RCD is a first RCD output and the plurality of volatile memories is a first plurality of volatile memories, the RCD further includes a second RCD output, and the apparatus further comprises a second plurality of volatile memories and a second C/A multiplexer including a third C/A mux input coupled to the second RCD output, a fourth C/A mux input coupled to the controller, and a second C/A mux output coupled to the second plurality of volatile memories.
5 more elements
An apparatus, comprising:
- a plurality of volatile memories;
- a non-volatile memory;
- a controller coupled to the non-volatile memory;
- a registering clock driver (RCD);
- a command/address (C/A) multiplexer including a first C/A mux input coupled to an output of the RCD, a second C/A mux input coupled to the controller, and a C/A mux output coupled to the plurality of volatile memories;
- and
- a data multiplexer including a first data mux input coupled to an external connector of the apparatus, a second data mux input coupled to the controller, and a data mux output coupled to at least one of the plurality of volatile memories, wherein the RCD is a first RCD and the plurality of volatile memories is a first plurality of volatile memories, and wherein the apparatus further comprises a second plurality of volatile memories, a second RCD, and a second C/A multiplexer including a third C/A mux input coupled to an output of the second RCD, a fourth C/A mux input coupled to the controller, and a second C/A mux output coupled to the second plurality of volatile memories.
4 more elements
A memory module, comprising:
- a connector configured to couple the memory module to a host data bus and a host command/address bus;
- a non-volatile memory;
- a controller coupled to the non-volatile memory;
- a plurality of volatile memories;
- a registering clock driver (RCD) including a first RCD output and a first RCD input coupled to the connector and configured to be coupled to the host command/address bus by the connector;
- a command/address (C/A) multiplexer including a first C/A mux input coupled to the first RCD output, a second C/A mux input coupled to the controller, and a first C/A mux output coupled to the first plurality of volatile memories;
- and
- a data multiplexer including a first data mux input configured to be coupled to the host data bus by the connector, a second data mux input coupled to the controller, and a data mux output coupled to at least one of the plurality of volatile memories,
- wherein the plurality of volatile memories is a first plurality of volatile memories and the RCD further includes a second RCD output, further comprising a second plurality of volatile memories and a second C/A multiplexer including a third C/A mux input coupled to the second RCD output, a fourth C/A mux input coupled to the controller, and a second C/A mux output coupled to the second plurality of volatile memories.
6 more elements
A memory module, comprising:
- a connector configured to couple the memory module to a host data bus and a host command/address bus;
- a non-volatile memory;
- a controller coupled to the non-volatile memory;
- a plurality of volatile memories;
- a registering clock driver (RCD) including a first RCD output and a first RCD input coupled to the connector and configured to be coupled to the host command/address bus by the connector;
- a command/address (C/A) multiplexer including a first C/A mux input coupled to the first RCD output, a second C/A mux input coupled to the controller, and a first C/A mux output coupled to the first plurality of volatile memories;
- and
- a data multiplexer including a first data mux input configured to be coupled to the host data bus by the connector, a second data mux input coupled to the controller, and a data mux output coupled to at least one of the plurality of volatile memories,
- wherein the RCD is a first RCD and the plurality of volatile memories is a first plurality of volatile memories, and wherein the apparatus further comprises a second plurality of volatile memories, a second RCD, and a second C/A multiplexer including a third C/A mux input coupled to an output of the second RCD, a fourth C/A mux input coupled to the controller, and a second C/A mux output coupled to the second plurality of volatile memories.
6 more elements
An apparatus, comprising:
- a substrate;
- a connector on the substrate, the connector configured to receive first command/address signals and first data signals;
- a controller on the substrate, the controller configured to generate second command/address signals and second data signals;
- at least one registering clock driver on the substrate;
- and
- a first plurality of memories on the substrate;
- a second plurality of memories on the substrate,
- wherein each of the first plurality of memories is configured to receive the first command/address signals from the connector through a first RCD output of the at least one registering clock driver and to receive the second command/address signals from the controller without intervening the registering clock driver therebetween,
- wherein each of the second plurality of memories is configured to receive the first command/address signals from the connector through a second RCD output of the at least one registering clock driver and to receive the second command/address signals from the controller without intervening the registering clock driver therebetween,
- wherein each of the first plurality of memories is configured to receive the first data signals from the connector and the second data signals from the controller through a corresponding first data multiplexer, and
- wherein each of the second plurality of memories is configured to receive the first data signals from the connector and the second data signals from the controller through a corresponding second data multiplexer.
8 more elements
Dependencies are inferred from the claim text.