Semiconductor package including workpiece and method for fabricating the semiconductor package

A method for fabricating a semiconductor package, comprising:

• providing a first workpiece, wherein the first workpiece comprises a first substrate and a plurality of first rewiring structures arranged on the first substrate at intervals, and each of the plurality of first rewiring structures comprises at least two first rewiring layers;
• forming an encapsulation layer on the plurality of first rewiring structures, wherein the encapsulation layer is provided with a plurality of first through holes, and the plurality of first through holes exposes one first rewiring layer;
• disposing at least two second rewiring layers on a side of the encapsulation layer facing away from the plurality of first rewiring structures, wherein the at least two second rewiring layers are electrically connected to the exposed first rewiring layer;
• removing the first substrate;
• providing a plurality of semiconductor elements, and arranging the plurality of semiconductor elements on a side of the plurality of first rewiring structures facing away from the encapsulation layer, wherein the at least two first rewiring layers are electrically connected to pins of the plurality of semiconductor elements;
• and
• performing cutting based on each of the plurality of semiconductor elements to obtain a plurality of semiconductor packages;
• wherein providing the first workpiece comprises:
• providing the first substrate;
• providing the plurality of first rewiring structures;
• and
• arranging the plurality of first rewiring structures on the first substrate at intervals;
• wherein each of the plurality of first rewiring structures further comprises a first alignment mark;
• wherein after providing the first substrate and before arranging the plurality of first rewiring structures on the first substrate at intervals, the method further comprises one of the following:
• forming second alignment marks on the first substrate, wherein each of the second alignment marks is arranged corresponding to the first alignment mark:
• forming a temporary insulating layer on the second alignment marks;
• or
• forming a temporary insulating layer on the first substrate;
• and forming second alignment marks on the temporary insulating layer, wherein the second alignment marks are arranged corresponding to first alignment marks;
• and
• wherein arranging the plurality of first rewiring structures on the first substrate at intervals comprises:
• arranging the plurality of first rewiring structures on the temporary insulating layer at intervals.