Efficient redistribution layer topology
AssigneeTexas Instruments Incorporated
InventorsVivek Swaminathan Sridharan, Christopher Daniel Manack, Joseph Liu
Life of this patent
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Abstract
In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.
Claims23
A chip scale package (CSP), comprising:
- a semiconductor die;
- a passivation layer abutting the semiconductor die;
- a via extending through the passivation layer;
- a first metal layer abutting the via;
- an insulation layer abutting the first metal layer, the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2;
- and
- a second metal layer abutting the insulation layer and adapted to couple to a solder ball, the second metal layer abutting the first metal layer at a point of contact defined by the orifice in the insulation layer, wherein:
- the passivation layer has a first passivation layer surface and a second passivation layer surface opposing the first passivation layer surface,
- the via has a first via surface and a second via surface opposing the first via surface, and
- the first passivation layer surface is approximately flush with the first via surface and the second passivation layer surface is approximately flush with the second via surface.
An electronic device, comprising:
- a printed circuit board (PCB);
- a solder ball coupled to the PCB;
- and
- a chip scale package (CSP) coupled to the solder ball, the CSP including:
- a semiconductor die;
- a passivation layer abutting the semiconductor die;
- a first via extending through the passivation layer, the first via having first and second surfaces that are approximately flush with first and second surfaces, respectively, of the passivation layer;
- a second via extending through the passivation layer, the second via having first and second surfaces that are approximately flush with the first and second surfaces, respectively, of the passivation layer;
- a first metal layer abutting the first via;
- an insulation layer abutting the first metal layer and having first and second orifices, each of the first and second orifices having a maximal horizontal area of less than 750 microns2;
- a second metal layer abutting the first metal layer through the first orifice;
- and
- a third metal layer abutting the second via, the second metal layer abutting the third metal layer through the second orifice,
- wherein the first and second vias are vertically aligned with the second metal layer.
A chip scale package (CSP), comprising:
- a semiconductor die;
- a passivation layer abutting the semiconductor die;
- a first metal layer coupled to the semiconductor die by a first via in the passivation layer;
- a second metal layer coupled to the semiconductor die by a second via in the passivation layer;
- an insulation layer isolating the first and second metal layers from each other, wherein the insulation layer includes an orifice having a maximal horizontal area of 350 microns2;
- and
- a third metal layer coupled to the first metal layer through the orifice,
- wherein the first and second vias are vertically aligned with the third metal layer.
Dependencies are inferred from the claim text.