Semiconductor devices including cobalt alloys and fabrication methods thereof

A 3-D V-NAND memory device comprising a semiconductor device and including

• a selection gate,
• a word line staircase contact, and
• a source line contact,
• wherein the semiconductor device comprises:
• a substrate;
• a conductive wiring which comprises cobalt and is electrically connected to the substrate;
• an insulating material which electrically isolates the conductive wiring from neighboring wiring;
• and
• a first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material, and
• wherein the selection gate, word line staircase contact, and source line contact each comprise the conductive wiring and the first barrier layer of the semiconductor device.

A method of forming a semiconductor metallization interconnect for a semiconductor device, comprising:

• forming at least one cobalt alloy with a cobalt content ranging from 30% to 99%;
• and
• depositing the at least one cobalt alloy onto source and drain regions after Local-Inter-Connect etch or Local-Inter-Connect clean to act as a low resistance metal contact to the source and drain regions of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET),
• wherein the source and drain regions comprise at least one of Si, Ge, SiGe, SiC, and a III-V based semiconductor,
• wherein atomic interaction of Ti in Co—Ti alloy with the source and drain regions forms a diffusion barrier to block metals from subsequent penetrating into the source and drain regions,
• wherein a height of a fundamental Metal-Semiconductor junction Schottky barrier is reduced to decrease the fundamental Metal-Semiconductor junction Schottky barrier to a current flow from a channel of the MOSFET to the contact or the Local-Inter-Connect, and
• wherein the semiconductor device comprises:
• a substrate;
• a conductive wiring which comprises cobalt and is electrically connected to the substrate;
• an insulating material which electrically isolates the conductive wiring from neighboring wiring;
• and
• a first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material.

A method of controlling a work-function of a semiconductor metallization interconnect for a semiconductor device, comprising:

• depositing at least one cobalt alloy onto a gate dielectric layer of an NMOS transistor, wherein the at least one cobalt alloy acts as a work-function gate electrode for the NMOS transistor;
• depositing at least one cobalt alloy onto a gate dielectric layer of a PMOS transistor, wherein the at least one cobalt alloy acts as a work-function gate electrode for the PMOS transistor;
• and
• depositing at least one cobalt alloy as a liner onto each of the work-function gate electrodes to surround a core space and fill the core space with cobalt, forming the semiconductor metallization interconnect including the core filled with cobalt and the liner,
• wherein the work-function of the semiconductor metallization interconnect is controlled to be a value in a range from 4.2 eV to 5.2 eV, and
• wherein the semiconductor device comprises:
• a substrate;
• a conductive wiring which comprises cobalt and is electrically connected to the substrate;
• an insulating material which electrically isolates the conductive wiring from neighboring wiring;
• and
• a first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material.