Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

An integrated circuit structure, comprising:

• a transistor device, the transistor device having a source/drain contact;
• a first interconnect line above but not over the source/drain contact, the first interconnect line having a bottom surface and an uppermost surface;
• a second interconnect line above and over the source/drain contact, the second interconnect line above but not over the first interconnect line;
• a through via structure directly electrically connecting the second interconnect line to the source/drain contact, the through via structure laterally adjacent to but not in contact with the first interconnect line, the through via structure comprising a conductive barrier layer continuous from the second interconnect line to the source/drain contact, and the through via structure comprising a conductive fill material within the conductive barrier layer, the conductive fill material continuous from the second interconnect line to the source/drain contact, the through via structure having substantially straight sidewalls from the second interconnect line to the source/drain contact, and the through via structure having an uppermost surface above the uppermost surface of the first interconnect line, wherein the source/drain contact extends laterally beyond the sidewalls of the through via structure;
• a first dielectric material portion below the first interconnect line and above the transistor device, the first dielectric material portion laterally adjacent to the through via structure;
• a second dielectric material portion laterally between the through via structure and the first interconnect line;
• and
• a third dielectric material portion over and in contact with the first interconnect line, wherein the third dielectric material portion, the second dielectric material portion and the first dielectric material portion are continuous with one another.