US 11,380,614 B2Granted

Circuit assembly

AssigneeAP Memory Technology Corp.

InventorsWenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien-An Yu, Chun Yi Lin

Life of this patent

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Abstract

A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

Claims15

Dependent claims

A circuit assembly, comprising:

an integrated circuit (IC) die, providing an IC and comprising a plurality of first conductive pads at least one of which electrically connects to the IC;
and
a first capacitor die, having a first side and a second side that is opposite to the first side, providing a plurality of capacitors and comprising a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side, at least one of the second conductive pads electrically connecting to the capacitors, and the conductive vias being adapted to form a plurality of external signal connections of the IC die and the first capacitor die;
wherein the IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/010,517Filed 2 Sep 2020 · continuation in part
Priority: 26 Dec 2018
Published: US 2020/0212027 A124 Dec 2020
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

H10W 20/496
Capacitive arrangements or effects of, or between wiring layers: capacitor integral with wiring layers
H10W 90/00
Package configurations
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Family

Application16/232,417Parent of this continuation-in-part · filed 26 Dec 2018
Application62/895,467Us provisional application · filed 3 Sep 2019
US 2020/0402903 A1Pre-grant publication · published 24 Dec 2020
US 10,811,402 B2Parent of this continuation-in-part
US 2020/0212027 A1Published application
US 11,380,614 B2This patent

From the US filing history. Foreign family members aren’t listed.