Semiconductor wafer, method for separating the semiconductor wafer, semiconductor chip, and semiconductor package including the semiconductor chip
AssigneeSK hynix Inc.
InventorHyun Chul Seo
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Abstract
A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed.
Claims17
A semiconductor chip, which includes an upper surface, a first side surface, and a second side surface positioned opposite to the first side surface, comprising:
- a test pad disposed on the upper surface and in an edge region adjacent to the first side surface;
- a chip pad disposed on the upper surface and in an edge region adjacent to the second side surface;
- and
- a protective layer covering the upper surface and leaving at least a portion of the chip pad exposed,
- wherein the test pad includes an overlapping portion overlapping the upper surface and a protruding portion protruding from the first side surface toward an outside of the semiconductor chip, and
- wherein the protective layer covers at least a portion of the overlapping portion of the test pad.
A semiconductor package comprising:
- a substrate;
- and
- a plurality of semiconductor chips stacked in a vertical direction over the substrate, each of the plurality of semiconductor chips having an upper surface, a first side surface, and a second side surface positioned opposite to the first side surface,
- wherein each of the plurality of semiconductor chips comprises:
- a test pad disposed on the upper surface and in an edge region of the semiconductor chip adjacent to the first side surface;
- and
- a chip pad disposed on the upper surface and in an edge region of the semiconductor chip adjacent to the second side surface,
- wherein the test pad for each of the semiconductor chips includes an overlapping portion overlapping the upper surface and a protruding portion protruding from the first side surface toward an outside of the semiconductor chip, and
- wherein each of the plurality of semiconductor chips further includes a protective layer covering the upper surface and leaving at least a portion of the chip pad exposed, and the protective layer covers at least a portion of the overlapping portion of the test pad.
Dependencies are inferred from the claim text.