Method for manufacturing nanostructure with various widths

A method for manufacturing a semiconductor structure, comprising:

• alternately stacking sacrificial layers and semiconductor layers over a substrate;
• forming a first mask structure over a first region of the substrate and a second mask structure over a second region of the substrate;
• forming a first spacer and a second spacer on opposite sidewalls of the second mask structure;
• etching the sacrificial layers and semiconductor layers not covered by the first mask structure, the second mask structure, the first spacer, and the second spacer to form a first fin structure and a second fin structure, wherein a sidewall of the first fin structure is aligned with a sidewall of the first mask structure, and a first sidewall of the second fin structure is aligned with a sidewall of the first spacer,
• removing the sacrificial layers in the first fin structure to form first gaps between the semiconductor layers in the first fin structure;
• and
• removing the sacrificial layers in the second fin structure to form second gaps between the semiconductor layers in the second fin structure.

A method for manufacturing a semiconductor structure, comprising:

• alternately stacking sacrificial layers and semiconductor layers over a substrate to form a semiconductor stack;
• forming a first mask structure and a second mask structure over the semiconductor stack;
• forming a first spacer on a first sidewall of the second mask structure and a second spacer on a second sidewall of the second mask structure;
• patterning the semiconductor stack through the first mask structure to form a first fin structure;
• patterning the semiconductor stack through the second mask structure, the first spacer, and the second spacer to form a second fin structure;
• removing the sacrificial layers of the first fin structure to form first nanostructures and removing the sacrificial layers of the second fin structure to form second nanostructures;
• forming a first gate structure wrapping around the first nanostructures, wherein a bottom surface of the first gate structure is not flat.