Mechanisms for forming FinFET device

A method for forming a semiconductor device, the method comprising:

• forming a first fin and a second fin over a substrate;
• depositing a gate electrode layer over the first fin, the second fin, and the substrate;
• and
• performing an etching process, wherein the etching process partially removes the gate electrode layer to form a first gate electrode over the first fin, a second gate electrode over the second fin, and a dummy gate electrode over the substrate between the first fin and the second fin, wherein a lower portion of the dummy gate electrode is narrower than an upper portion of the dummy gate electrode, wherein a lower portion of the first gate electrode is wider than an upper portion of the first gate electrode.

A method for forming a semiconductor device, the method comprising:

• forming a first fin over a substrate;
• forming a gate electrode layer over the first fin and the substrate;
• performing a first etching process to remove an upper portion of the gate electrode layer disposed over an upper surface of the first fin, the first etching process forming an upper portion of a first gate electrode over the first fin and forming an upper portion of a dummy gate electrode adjacent to the first fin, the upper portion of the first gate electrode being spaced from the upper portion of the dummy gate electrode by a first distance;
• and
• performing a second etching process different from the first etching process to remove a lower portion of the gate electrode layer, the second etching process forming a lower portion of the first gate electrode and a lower portion of the dummy gate electrode, the lower portion of the first gate electrode being spaced from the lower portion of the dummy gate electrode by a second distance different from the first distance, the first distance and the second distance being measured along a direction parallel to a major upper surface of the substrate, wherein the second etching process removes portions of the gate electrode layer disposed under the upper portion of the dummy gate electrode to form a recess, wherein a first width of the lower portion of the dummy gate electrode is smaller than a second width of the upper portion of the dummy gate electrode, and wherein a third width of the lower portion of the first gate electrode is larger than a fourth width of the upper portion of the first gate electrode.