US 11,380,583 B2Granted

Forming self-aligned vias and air-gaps in semiconductor fabrication

AssigneeTessera, Inc.

InventorsLawrence A. Clevenger, Carl J. Radens, John H. Zhang

Life of this patent

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Abstract

A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

Claims21

Dependent claims

A method comprising:

providing a substrate;
providing a structure disposed above the substrate, the structure comprising one or more material layers;
providing a plurality of spacers disposed above the structure, the plurality of spacers extending in a direction parallel to the substrate;
etching, using the plurality of spacers as a mask, (i) first trenches in the structure to a first level above the substrate and (ii) second trenches in the structure to the first level above the substrate, the second trenches alternating with the first trenches;
filling the first trenches and second trenches with a first material;
etching a plurality of first self-aligned via openings through the first material in the first trenches to a second level above the substrate, the second level being closer to the substrate than the first level;
filling the plurality of first self-aligned via openings with a second material;
etching a plurality of second self-aligned via openings through the first material in the second trenches down to approximately the second level above the substrate;
and
filling the plurality of second self-aligned via openings with a third material.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/181,399Filed 22 Feb 2021 · continuation
Priority: 29 Mar 2017
Published: US 2021/0202313 A11 Jul 2021
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10P 50/283
Of inorganic materials: by chemical means

Family

Application15/472,745Parent of this continuation · filed 29 Mar 2017
Application15/815,173Parent of this continuation · filed 16 Nov 2017
US 9,911,652 B1Parent of this continuation · filed 6 Mar 2018
Application16/257,221Parent of this continuation · filed 25 Jan 2019
US 10,242,911 B2Parent of this continuation · filed 26 Mar 2019
US 2021/0202313 A1Pre-grant publication · published 1 Jul 2021
US 10,930,553 B2Parent of this continuation
US 2018/0286750 A1Published application
US 2019/0172748 A1Published application
US 11,380,583 B2This patent

From the US filing history. Foreign family members aren’t listed.