Interconnect structures of semiconductor devices having a via structure through an upper conductive line

A method of fabricating an interconnect structure of a semiconductor device, the method comprising:

• forming a first dielectric layer over a first conductive line;
• forming a second conductive line over the first dielectric layer;
• forming a second dielectric layer over the first dielectric layer and adjacent to the second conductive line;
• forming a via opening through the second conductive line, wherein the via opening is aligned over the first conductive line and has a width equal to a width of the second conductive line;
• removing a portion of the first dielectric layer beneath the via opening to extend the via opening to an upper surface of the first conductive line before filling the via opening with a conductive material to form an interconnect via, wherein extending of the via opening to the upper surface of the first conductive line comprises an etching process, wherein the first dielectric layer and the second dielectric layer are etched by the etching process, wherein the second dielectric layer etches slower than the first dielectric layer during the etching process;
• and
• filling the via opening with the conductive material to form the interconnect via, wherein an upper portion of the interconnect via forms a portion of the second conductive line.