Loading patent…
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunchul Yoon, Mincheol Kwak, Joonghee Kim, Jihee Kim, Yeongshin Park, Jungheun Hwang
Estimating the term…
In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.
A method of manufacturing an integrated circuit device including a plurality of memory cells connected to a plurality of bit lines, the method comprising:
A method of manufacturing an integrated circuit device including a plurality of memory cells connected to a plurality of bit lines, the method comprising:
A method of manufacturing an integrated circuit device including a plurality of memory connected to a plurality of bit lines, the method comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
For Group IV materials or Group III-V materials: characterised by their composition, e.g. multilayer masks or materials
Characterised by their sizes, orientations, dispositions, behaviours or shapes: characterised by the processes involved to create the masks
Data lines or contacts therefor: bit lines
Characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane: characterised by the process involved…
About 13 years 6 months of term left · ends 25 Apr 2040 (estimated)
This application claims the benefit of Korean Patent Application No. 10-2019-0121726, filed on Oct. 1, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
The inventive concept relates to a method of manufacturing an integrated circuit device, and more particularly, to a method of manufacturing an integrated circuit device capable of reducing process defects caused by rework in a photolithography process for manufacturing processes of the integrated circuit device.
Recently, as down-scaling of an integrated circuit device is rapidly proceeding, a feature size of the integrated circuit device is refined and a line width of each of patterns that form the integrated circuit device is gradually reduced. Therefore, when patterns having various shapes, sizes, and densities used for the integrated circuit device are simultaneously formed, process difficulty increases. In particular, when a rework process for removing a photoresist pattern and forming a new photoresist pattern is performed since defects occur in the photoresist pattern obtained after performing a photolithography process for manufacturing the integrated circuit device, it is necessary to develop a rework process in which lower structures, an etched layer, or hard mask layers left on a substrate are not damaged by a rework atmosphere and the rework process may be stably performed.
Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic plan view illustrating an exemplary configuration of an integrated circuit device that may be obtained by a method of manufacturing an integrated circuit device according to example embodiments of the inventive concept;
FIG. 2A is a view illustrating a plurality of island patterns that may be implemented in a plurality of chip regions of an integrated circuit device that may be obtained by a method of manufacturing an integrated circuit device according to example embodiments of the inventive concept. In FIG. 2A, (a) is a perspective view illustrating parts of the plurality of chip regions and (b) is a plan view illustrating a plane arrangement of the plurality of island patterns illustrated in (a);
Hereinafter, various example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements throughout.
FIG. 1 is a schematic plan view illustrating an integrated circuit device 100 that may be obtained by a method of manufacturing an integrated circuit device according to example embodiments of the inventive concept.
Referring to FIG. 1, the integrated circuit device 100 includes a substrate 110 having a plurality of chip regions CR and a scribe lane region SLR that surrounds the plurality of chip regions CR. On the substrate 110, the plurality of chip regions CR may be arranged in a matrix. The scribe lane region SLR may include a cutting area for individualizing the plurality of chip regions CR.