Multi-layer chip ceramic dielectric capacitor

A multi-layer chip ceramic dielectric capacitor, comprising:

• a ceramic dielectric layer;
• a plurality of first electrode layers embedded in the ceramic dielectric layer, wherein each of the first electrode layers comprises a first internal electrode, a second internal electrode and a third internal electrode, which are spaced apart successively and located in a same plane, and the first internal electrode and the third internal electrode are exposed to two ends of the ceramic dielectric layer;
• a plurality of second electrode layers embedded in the ceramic dielectric layer, wherein the plurality of second electrode layers and the plurality of first electrode layers are alternately arranged at intervals, and each of the second electrode layers comprises a fourth internal electrode and a fifth internal electrode, which are spaced apart and located in a same plane;
• external electrodes coated at the two ends of the ceramic dielectric layer, wherein two external electrodes are in electrical contact with the first internal electrode and the third internal electrode, respectively,
• wherein one end of the fourth internal electrode is corresponding to an adjacent first internal electrode, and forms a first capacitance component, and the other end of the fourth internal electrode is corresponding to an adjacent second internal electrode, and forms a second capacitance component, one end of the fifth internal electrode is corresponding to the adjacent second internal electrode, and forms a third capacitance component, and the other end of the fifth internal electrode is corresponding to an adjacent third internal electrode, and forms a fourth capacitance component, and the first capacitance component, the second capacitance component, the third capacitance component and the fourth capacitance component are successively connected in series,
• a first electrode gap between the first internal electrode and the adjacent second internal electrode is D1, a second electrode gap between the second internal electrode and the adjacent third internal electrode is D2, and a third electrode gap between the fourth internal electrode and an adjacent fifth internal electrode is D3, wherein D1=D2=D3, and
• a fourth electrode gap between the fourth internal electrode and an adjacent external electrode is L1, and a fifth electrode gap between the fifth internal electrode and an adjacent external electrode is L2, wherein L1=L2.