Chip electronic component and electronic component mounting structure

A chip electronic component, comprising:

• a stack including a plurality of ceramic layers that are stacked and a plurality of inner electrodes stacked on the plurality of ceramic layers, the stack including:
• a first main surface and a second main surface opposed each other in a thickness direction of the stack;
• a first lateral surface and a second lateral surface opposed each other in a width direction of the stack perpendicular or substantially perpendicular to the thickness direction;
• and
• a first end surface and a second end surface opposed each other in a length direction of the stack perpendicular to the thickness direction and the width direction;
• a first external electrode disposed at least on the first end surface and the first main surface of the stack;
• a second external electrode disposed at least on the second end surface and the first main surface of the stack;
• a first bump electrically connected to the first external electrode;
• and
• a second bump electrically connected to the second external electrode;
• wherein
• the first bump is disposed at least on a portion of the first external electrode on the first main surface;
• the second bump is disposed at least on a portion of the second external electrode on the first main surface;
• the first bump includes a portion that is in contact with the first external electrode;
• the second bump includes a portion that is in contact with the second external electrode;
• and
• the first bump and the second bump each have a porosity greater than or equal to about 5% and less than or equal to about 40%.