Methods to limit power during stress test and other limited supplies environment

A method of operating a memory device, the method comprising:

• initiating a boot phase of a memory controller of the memory device, wherein operating instructions are loaded into processing circuitry of the memory controller during the boot phase;
• detecting a decrease in a circuit supply voltage of the memory controller during the boot phase;
• and
• activating a low power mode of a memory controller in response to the detection of the decrease in the circuit supply voltage.

An electronic system comprising:

• a power supply;
• and
• multiple memory devices receiving power from the power supply, the memory devices including:
• multiple memory dies;
• and
• a memory controller operatively coupled to the memory dies, the memory controller including:
• a processor core configured to execute instructions to control the multiple memory dies;
• voltage detector circuitry configured to detect a decrease in supply voltage to the memory controller during a boot phase of the memory devices;
• and
• logic circuitry configured to enter a low power mode in response to detecting the decrease in the supply voltage.

An electronic system comprising:

• a power supply;
• a power supply voltage monitor circuit;
• a system controller including processor circuitry including one or more processors;
• and
• multiple memory devices operatively coupled to the system controller and receiving power from the power supply, the memory devices including:
• multiple memory dies;
• and
• a memory controller operatively coupled to the memory dies, the memory controller including a processor core configured to execute instructions to control the memory dies;
• wherein the system controller is configured to perform operations including:
• providing a low power control signal to one or more memory devices in response to the power supply monitor circuit detecting a decrease in supply voltage of the power supply;
• and
• wherein the memory controller of the one or more memory devices is configured to enter a low power mode in response to the low power control signal.