Circuit to reduce gating overall system performance

A storage device, comprising:

• one or more memory planes each partitioned into consecutive chunks, each chunk arranged as sequential columns of memory cells having a starting address stored in first registers;
• and
• control logic configured, during a power-on-read (POR) operation, to:
• identify information comprising bad physical addresses in each plane;
• determine, for each chunk in each plane based on the corresponding starting address and the bad physical address information, a pointer to a memory location;
• and
• store the pointers in second registers for use with the starting addresses in performing register reads.

A storage device, comprising:

• a plurality of consecutive memory chunks each arranged as columns of memory cells;
• first registers configured to store an initial column address for each chunk;
• and
• control logic configured, during a power-on-read (POR) operation, to:
• identify bad physical addresses in each chunk;
• retrieve, from the first registers for each successive chunk, the starting column address;
• determine a pointer to a memory location for the initial column address for each block, wherein at least some of the pointers are shifted based on the bad physical addresses;
• and
• store the pointers in second registers for use in register read operations.