TSV auto repair scheme on stacked die
AssigneeMicron Technology, Inc.
InventorNaohisa Nishioka
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Abstract
Disclosed herein is an apparatus that includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to an associated one of the pad electrodes, a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to an associated one of the TSVs, and a training circuit configured to perform a training operation on a signal path including the selected one of the pad electrodes and the selected one of the TSVs. The training circuit is configured to activate a fail signal when the signal path is determined to be defective. The fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits.
Claims20
An apparatus comprising:
- a first semiconductor chip including a plurality of pad electrodes, a plurality of first latch circuits assigned to an associated one of the plurality of pad electrodes, and a spare pad electrode;
- and
- a second semiconductor chip including a plurality of TSVs each electrically coupled to an associated one of the plurality of pad electrodes to form a plurality of signal paths, a plurality of second latch circuits assigned to an associated one of the TSVs, and a spare TSV,
- wherein the first semiconductor chip further includes a comparison circuit configured to compare a potential of a signal path of the plurality of signal paths with a reference potential and provide a fail signal based on the comparison, wherein the fail signal is indicative of a defect in the signal path and is provided to the first semiconductor chip and the second semiconductor chip, and wherein responsive to the fail signal, the defective signal path is invalidated and a spare signal path including the spare pad electrode and the spare TSV is validated.
A method comprising:
- activating a row selection signal and a column selection signal in synchronization with a test clock signal in a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip includes a plurality of TSVs arranged in row and column directions and a plurality of first latch circuits, each first latch circuit of the plurality of first latch circuits corresponding to a respective of the plurality of TSVs and wherein the second semiconductor chip includes a control circuit and a plurality of pads coupled correspondingly to the plurality of TSVs;
- testing a plurality of signal paths between the first semiconductor chip and the second semiconductor chip;
- and
- activating a fail signal indicative of a defective signal path and latching the fail signal into corresponding ones of the latch circuits in the first semiconductor chip and the second semiconductor chip.
An apparatus comprising:
- a first semiconductor chip including a plurality of pad electrodes and a first switch circuit;
- a second semiconductor chip stacked on the first semiconductor chip, wherein the second semiconductor chip including a second switch circuit and a plurality of TSVs comprising a spare TSV, each TSV of the plurality of TSVs coupled to an associated one of the plurality of pad electrodes to form a plurality of signal paths, the second semiconductor chip further including a selection circuit configured to selectively activate the spare TSV, wherein the selection circuit comprises:
- a first transistor coupled to the plurality of TSVs;
- a first gate circuit configured to provide a TSV selection signal to the first transistor based on corresponding TSV row and column selection signals and a core selection signal;
- and
- a second gate circuit configured to control a corresponding latch circuit included in the second switch circuit.
Dependencies are inferred from the claim text.