Duty adjustment circuit, semiconductor storage device, and memory system
AssigneeKioxia Corporation
InventorMasashi Nakata
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a duty adjustment circuit includes: a first delay circuit including a plurality of first delay elements connected in series, each of the first delay elements has a first delay amount; a second delay circuit having a first variable delay unit configured to set a second delay amount smaller than the first delay amount; and a third delay circuit having a second variable delay unit configured to set a third delay amount smaller than the first delay amount. An output terminal of the second delay circuit is connected to an even numbered one of the first delay elements, and an output terminal of the third delay circuit is connected to an odd numbered one of the first delay elements.
Claims13
A duty adjustment circuit comprising:
- a first delay circuit including a plurality of first delay elements connected in series, wherein each of the first delay elements has a first delay amount;
- a second delay circuit having a first variable delay unit configured to set a second delay amount smaller than the first delay amount;
- and
- a third delay circuit having a second variable delay unit configured to set a third delay amount smaller than the first delay amount,
- wherein an output terminal of the second delay circuit is connected to an even numbered one of the first delay elements, and an output terminal of the third delay circuit is connected to an odd numbered one of the first delay elements.
A semiconductor storage device comprising:
- an interface chip provided with a duty adjustment circuit that includes:
- a first delay circuit including a plurality of first delay elements connected in series, wherein each of the first delay elements has a first delay amount;
- a second delay circuit having a first variable delay unit configured to set a second delay amount smaller than the first delay amount;
- and
- a third delay circuit having a second variable delay unit configured to set a third delay amount smaller than the first delay amount,
- wherein an output terminal of the second delay circuit is connected to an even numbered one of the first delay elements, and an output terminal of the third delay circuit is connected to an odd numbered one of the first delay elements;
- and
- a non-volatile memory chip including a plurality of memory cells formed as a memory cell array,
- wherein the duty adjustment circuit adjusts a duty ratio of a read enable signal or a data strobe signal communicated between a controller and the non-volatile memory chip.
A method comprising:
- receiving a code signal indicating a pulse width of an input clock signal and a pulse width of an inversion logic of the input clock signal;
- counting a first number of high-level bits of the signal during a first cycle of the code signal;
- counting a second number of high-level bits of the signal during a second cycle of the code signal;
- determining a difference between the first number and second number;
- and
- determining, based on the determination, whether to update the code signal.
Dependencies are inferred from the claim text.