US 11,380,404 B2Granted

Memory device and method of reading data

AssigneeSamsung Electronics Co., Ltd.

InventorsSu Chang Jeon, Seung Bum Kim, Ji Young Lee

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Abstract

A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Claims20

Dependent claims

A non-volatile memory, comprising:

a memory cell region extending in a first horizontal direction and including a first outer region proximate a first end of the memory cell region, an inner region separated from the first end by the first outer region, and a second outer region proximate a second end of the memory cell region, wherein an arrangement of the first end, the first outer region, the inner region, the second outer region and the second end extends in a second horizontal direction that is orthogonal to the first horizontal direction;
an inner memory cell string including memory cells of the memory cell region that are connected to an inner pillar extending vertically upward through the inner region;
outer memory cell strings including memory cells of the memory cell region that are connected to first outer pillars extending vertically upward through the first outer region and memory cells of the memory cell region that are connected to second outer pillars extending vertically upward through the second outer region;
a first bit line connected to the inner pillar and extending in the second horizontal direction;
second bit lines respectively connected to the first and second outer pillars and extending in the second horizontal direction;
and
a page buffer circuit including a first latch and a second latch,
wherein the first latch is connected to the first bit line and configured to sense first data in the inner memory cell string using a first sensing developing time, and
the second latch is connected to a second bit line from among the second bit lines and configured to sense second data in an outer memory cell string from among the outer memory cell strings that is connected to the second bit line, wherein data of the outer memory cell strings are sensed using a second sensing developing time different from the first sensing developing time.

6 more elements

A non-volatile memory, comprising:

a memory cell region extending in a first horizontal direction and including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, wherein an arrangement of the first end, the outer region and the inner region extends in a second horizontal direction that is orthogonal to the first horizontal direction;
an inner memory cell string including memory cells of the memory cell region that are connected to an inner pillar extending vertically upward through the inner region;
an outer memory cell string including memory cells of the memory cell region that are connected to an outer pillar extending vertically upward through the outer region;
a first bit line connected to the inner pillar and extending in the second horizontal direction;
a second bit line connected to the outer pillar and extending in the second horizontal direction;
and
a data input/output (I/O) circuit comprising
a first page buffer circuit connected to the first bit line, and
a second page buffer circuit connected to the second bit line,
wherein the first page buffer circuit includes a first latch configured to sense first data in the inner memory cell string using a first sensing developing time, and a second latch configured to sense second data in the inner memory cell string using a second sensing developing time different from the first sensing developing time, and
the second page buffer circuit includes a third latch configured to sense third data in the outer memory cell string using a third sensing developing time, and a fourth latch configured to sense fourth data in the outer memory cell string using a fourth sensing developing time different from the third sensing developing time.

8 more elements

A method of reading data in a non-volatile memory including a memory cell region having a first end, a first outer region proximate the first end, an inner region separated from the first end by the first outer region, a second outer region proximate a second end of the memory cell region, first bit lines, a second bit line, an inner memory cell string including second memory cells connected to an inner pillar extending vertically upward through the inner region, outer memory cell strings including first memory cells connected to first outer pillars extending vertically upward through the first outer region and first memory cells connected to second outer pillars extending vertically upward through the second outer region, and a data input/output (I/O) circuit, the method comprising:

sensing first data stored in memory cells from among the first memory cells through a first bit line from among the first bit lines using a first sensing developing time, and
sensing second data stored in the second memory cells through the second bit line using a second sensing developing time, wherein data of the outer memory cell strings are sensed using the first sensing developing time that is different from the second sensing developing time.

Dependencies are inferred from the claim text.

Facts

Application: 17/099,678Filed 16 Nov 2020 · continuation
Priority: KR 10-2018-011303420 Sep 2018
Published: US 2021/0074364 A111 Mar 2021
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/12
Programming or data input circuits: programming voltage switching circuits
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits

Family

Application16/434,968Parent of this continuation · filed 7 Jun 2019
US 2021/0074364 A1Pre-grant publication · published 11 Mar 2021
US 10,867,682 B2Parent of this continuation
US 2020/0098433 A1Published application
US 11,380,404 B2This patent

From the US filing history. Foreign family members aren’t listed.