Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory controller performing the same

A nonvolatile memory device comprising:

• a memory block including a plurality of memory cells disposed in a vertical direction;
• and
• a control circuit configured to:
• perform an erase loop once or more on an entire of the memory block,
• perform a first partial verification operation on one or more groups of a plurality of groups in the memory block,
• determine whether a second partial verification operation is required for a group of the one or more groups, and
• perform the second partial verification operation on one or more subgroups of a plurality of subgroups in a group requiring the second partial verification operation among the plurality of groups,
• wherein the erase loop includes an erase operation and an erase verification operation,
• wherein the memory block is divided into the plurality of groups, and
• wherein the group requiring the second partial verification operation is divided into the plurality of subgroups.

A method of erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells being disposed in a vertical direction in each memory block, the method comprising:

• performing an erase loop once or more on an entire of a first memory block in the one or more memory blocks, the erase loop including an erase operation performed using an erase voltage and an erase verification operation performed using a first verification voltage having a first verification level;
• after the erase loop is successfully completed, performing a first partial verification operation on one or more groups of a plurality of groups in the first memory block using a first reference number and a second verification voltage having a second verification level different from the first verification level, the first memory block being divided into the plurality of groups;
• after the first partial verification operation is successfully completed, determining whether a second partial verification operation is required for a group of the one or more groups using a second reference number less than or equal to the first reference number;
• and
• performing the second partial verification operation on all or some of a plurality of subgroups in a group requiring the second partial verification operation among the plurality of groups using a third verification voltage having a third verification level different from the first verification level and a third reference number different from the first and second reference numbers, the group requiring the second partial verification operation being divided into the plurality of subgroups,
• wherein, when at least one of the first partial verification operation and the second partial verification operation has failed, the first memory block is indicated as a bad block.