US 11,380,401 B2 · High-voltage shifter with reduced transistor degradation

Abstract

Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

Claims20

Dependent claims

A voltage shifter for transferring a high-voltage input to memory cells in a memory device, the voltage shifter comprising:

an input port to receive the high-voltage input;
an output port coupled to one or more of the memory cells via an access line;
a high-voltage transistor coupled between the input port and the output port;
and
a transistor protection circuit, including at least one multiplexer configured to:
couple a bias voltage to the high-voltage transistor until a specific condition is satisfied;
and
after satisfaction of the specific condition, decouple the bias voltage from the high-voltage transistor, and couple a stress-relief signal to the high-voltage transistor to protect the high-voltage transistor from degradation due to a gate-to-channel stress during the transferring of the high-voltage input from the input port to the output port.

5 more elements

A memory device, comprising:

a group of memory cells;
and
a voltage shifter circuit, including:
an input port;
an output port;
a high-voltage transistor coupled between the input port and the output port and configured to transfer a high-voltage input received at the input port to one or more access lines coupled between the output port and one or more of the group of memory cells, the transferred high-voltage input being applied to the one or more memory cells to perform a memory operation;
a transistor protection circuit including at least one multiplexer configured to couple a bias voltage to the high-voltage transistor until a specific condition is satisfied, and, after satisfaction of the specific condition, to decouple the bias voltage from the high-voltage transistor and couple a stress-relief signal to the high-voltage transistor to protect the high-voltage transistor from degradation due to a gate-to-channel stress during the transferring of the high-voltage input from the input port to the output port;
and
a shifter control circuit configured to couple a shifter enabling signal to an inverter to enable the voltage transfer from the input port to the output port in response to a first state of the shifter enabling signal, and to disable the voltage transfer in response to a different second state of the shifter enabling signal.

6 more elements

Dependencies are inferred from the claim text.

High-voltage shifter with reduced transistor degradation

Life of this patent

High-voltage shifter with reduced transistor degradation

Life of this patent

Abstract

Claims20