Architecture for 3-D NAND memory

#Memory devices, such as flash memory, are widely used in computers and electronic products. Such memory devices usually have a memory array with numerous memory cells to store information. These memory devices also have circuitry to transfer information to and from the memory array. Information can be stored into the memory cells in a programming operation. The stored information can be retrieved in a read operation or can be cleared in an erase operation. In semiconductor memories, there is continuous pressure to reduce component dimensions and fit more components in a given amount of chip area. As dimensions shrink, various technical hurdles become more significant.

#FIG. 1 shows a block diagram of a memory device according to an embodiment of the invention.

#FIG. 2 shows a schematic diagram of a memory string device example according to an embodiment of the invention.

#FIG. 3 shows an isometric block diagram of a memory device according to an embodiment of the invention.

#In the following detailed description of various embodiments of the invention, reference is made to the accompanying drawings that form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made.

#The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on,” “side” (as in “sidewall”), “higher,” “lower,” “over,” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

#FIG. 1 shows a block diagram of an apparatus in the form of a memory device 100, having a memory array 102 with memory cells 103, according to an embodiment of the invention. Memory cells 103 can be arranged in rows and columns along with lines 104 and lines 106. Lines 104 can carry signals WL0 through WLm and can form part of access (e.g., word) lines of memory device 100. Lines 106 can carry signals BL0 through BLn and can form part of data lines (e.g., bit lines) of memory device 100.