Resistance change memory cell circuits and methods
AssigneeHefei Reliance Memory Limited
InventorBrent Steven Haukness
Life of this patent
Estimating the term…
Abstract
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
Claims20
A method of performing a memory operation in an integrated circuit memory device comprising a plurality of resistive change memory cells arranged in rows and columns of an array, wherein each of the plurality of resistive change memory cells includes an access transistor coupled to a first terminal of a resistive change memory element, and wherein a second terminal of the resistive change memory element is coupled to a bit line of the integrated circuit memory device and a gate of the access transistor is coupled to a word line of the integrated circuit memory device, the method comprising:
- applying, through one or more of the bit lines, one or more voltages to the second terminals of a plurality of the first resistive change memory cells arranged in a first row of the array, wherein the one or more voltages set resistive states of the first resistive change memory elements of the plurality of first resistive change memory cells to one or more initial resistance states;
- and
- applying, using a first current mirror, through a first word line, a first biasing current to gates of first access transistors of the plurality of first resistive change memory cells, wherein the first biasing current changes the resistive states of the first resistive change memory elements by limiting current through the first access transistors of the plurality of first resistive change memory cells.
A system for performing a memory operation in an integrated circuit memory device comprising a plurality of resistive change memory cells arranged in rows and columns of an array, wherein each of the plurality of resistive change memory cells includes an access transistor coupled to a first terminal of a resistive change memory element, and wherein a second terminal of the resistive change memory element is coupled to a bit line of the integrated circuit memory device and a gate of the access transistor is coupled to a word line of the integrated circuit memory device, the system comprising:
- a hardware processor;
- and
- a non-transitory machine-readable storage medium encoded with instructions executable by the hardware processor to perform operations comprising:
- causing application of one or more voltages, through one or more of the bit lines, to the second terminals of a plurality of first resistive change memory cells arranged in a first row of the array, wherein the one or more voltages set resistive states of the first resistive change memory elements of the plurality of first resistive change memory cells to one or more initial resistance states;
- and
- causing a current mirror to apply, through a first word line, a first biasing current to bias gates of first access transistors of the plurality of first resistive change memory cells, wherein the biasing current changes the resistive states of the first resistive change memory elements by limiting current through the second access transistors of the plurality of first resistive change memory cells.
A non-transitory machine-readable storage medium encoded with instructions executable by a hardware processor of a computing component, the machine-readable storage medium comprising instructions to cause the hardware processor to perform a method of performing a memory operation in an integrated circuit memory device comprising a plurality of resistive change memory cells arranged in rows and columns of an array, wherein each of the plurality of resistive change memory cells includes an access transistor coupled to a first terminal of a resistive change memory element, and wherein a second terminal of the resistive change memory element is coupled to a bit line of the integrated circuit memory device and a gate of the access transistor is coupled to a word line of the integrated circuit memory device, the method comprising:
- causing, through one or more of the bit lines, application of one or more voltages to the second terminals of a plurality of the first resistive change memory cells arranged in a first row of the array, wherein the one or more voltages set resistive states of the first resistive change memory elements of the plurality of first resistive change memory cells to one or more initial resistance states;
- and
- causing a current mirror to apply a first biasing current, through a first word line, to bias gates of first access transistors of the plurality of first resistive change memory cells, wherein the biasing current changes the resistive states of the first resistive change memory elements by limiting current through the plurality of first resistive change memory cells.
Dependencies are inferred from the claim text.