Access command delay using delay locked loop (DLL) circuitry
AssigneeMicron Technology, Inc.
InventorsJason M. Brown, Vijayakrishna J. Vankayala
Life of this patent
Estimating the term…
Abstract
Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.
Claims20
A device, comprising:
- a plurality of access lines arranged in a grid;
- a plurality of memory cells located at intersections of the access lines in the grid;
- a driver configured to transmit a corresponding signal to a memory cell of the plurality of memory cells in response to an access command;
- and
- a first delay locked loop (DLL) circuit configured to delay the access command by a first duration of time based on a timing difference between a reference clock signal and a data reference signal and based on a total delay associated with transmitting the reference clock signal through a first delay locked loop (DLL) clock tree, a data (DQ) driver, a data (DQ) pin, an input buffer, and a routing and buffering circuit.
A method, comprising:
- receiving, at a phase detector, a reference clock signal and a data reference signal;
- determining a phase difference between a transition of the reference clock signal and the data reference signal;
- transmitting a control signal from the phase detector to a delay line based on the phase difference;
- delaying, using the delay line, an access command in response to the control signal;
- and
- delaying a clock reference signal using an additional delay line disposed parallel to the delay line by a same amount as the access command is delayed.
A memory device, comprising:
- a memory array;
- a first delay locked loop (DLL) circuit configured to delay an access command;
- a second delay locked loop (DLL) circuit configured to delay a reference clock signal by a same amount as the first DLL circuit delays the access command;
- and
- a controller configured to access the memory array based on the access command.
Dependencies are inferred from the claim text.