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US 11,380,394 B2Granted
Voltage profile for reduction of read disturb in memory cells
AssigneeMicron Technology, Inc.
InventorsMingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
Life of this patent
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Abstract
An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.
Claims20
A device, comprising:
- at least one memory cell programmable to have a voltage threshold in a range;
- and
- at least one voltage driver coupled to the memory cell to drive up a voltage applied on the memory cell during reading of a state of the memory cell;
- wherein after the device starts sensing the state of the memory cell, the voltage driver is configured to reduce a profile of the voltage at a first rate toward a level in the range before further reducing the profile of the voltage at a second rate, greater than the first rate, toward zero.
1 more element
A method, comprising:
- programming a memory cell to have a voltage threshold in a range;
- and
- determining a state of the memory cell, including:
- driving up a voltage applied on the memory cell;
- sensing the state of the memory cell based on a current passing through the memory cell under the voltage;
- reducing a profile of the voltage at a first rate toward a level in the range before further reducing the profile of the voltage at a second rate, greater than the first rate, toward zero.
3 more elements
An apparatus, comprising:
- a controller;
- a first set of parallel wires disposed in a first layer of an integrated circuit die;
- a second set of parallel wires disposed in a second layer of the integrated circuit die;
- first voltage drivers connected to the first set of parallel wires respectively;
- second voltage drivers connected to the second set of parallel wires respectively;
- and
- an array of memory cells formed between the first layer and the second layer, wherein each respective memory cell is at a cross point of a wire in the first set and a wire in the second set;
- wherein during an operation to determine a state of the respective memory cell, at least one voltage driver in the first voltage drivers and the second voltage drivers is configured to:
- drive up a voltage applied on the memory cell;
- and
- reduce, a profile of the voltage at a first rate toward a level in a range during a first period of time;
- determine, during the first period of time, a level of a current passing through the memory cell;
- and
- reduce the profile of the voltage at a second rate, greater than the first rate, toward zero in a second period of time following the first period.
11 more elements
Dependencies are inferred from the claim text.