US 11,380,393 B2 · Memory device and method for coupling a main bitline to two points of a local bitline

Abstract

An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.

Claims20

Dependent claims

A non-volatile memory device comprising:

an array of memory cells arranged in rows and columns;
a plurality of local bitlines;
a plurality of main bitlines, wherein each same main bitline is coupleable to a corresponding subset of local bitlines, and wherein the memory cells of each column are coupled to a corresponding local bitline;
and
a column decoder, wherein the column decoder is electronically controllable to couple each same main bitline to a selected local bitline of the corresponding subset of local bitlines, and wherein the column decoder is configured to couple each same main bitline to two different points of the corresponding selected local bitline using a same respective select signal.

2 more elements

An electronic apparatus comprising:

a memory device comprising:
an array of memory cells arranged in rows and columns;
a plurality of local bitlines;
a plurality of main bitlines, wherein each same main bitline is coupleable to a corresponding subset of local bitlines, and wherein the memory cells of each column are coupled to a corresponding local bitline;
and
a column decoder, wherein the column decoder is electronically controllable to couple each same main bitline to a selected local bitline of the corresponding subset of local bitlines, and wherein the column decoder is configured to couple each same main bitline to two different points of the corresponding selected local bitline using a same respective select signal;
a controller;
and
a bus electrically coupling the controller and the memory device.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/129,016Filed 21 Dec 2020

Priority

IT 10201900002541123 Dec 2019

Published

US 2021/0193221 A124 Jun 2021

Granted

5 Jul 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 8/10
Arrangements for selecting an address in a digital store: decoders
G11C 13/0026
Address circuits or decoders: bit-line or column circuits
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out

Memory device and method for coupling a main bitline to two points of a local bitline

Life of this patent

Memory device and method for coupling a main bitline to two points of a local bitline

Life of this patent

Abstract

Claims20