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US 11,380,392 B2Granted
Resistive memory device with boundary and edge transistors coupled to edge bit lines
AssigneeSamsung Electronics Co., Ltd.
InventorMakoto Hirano
Life of this patent
Estimating the term…
Abstract
A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group.
Claims19
A resistive memory device comprising:
- a first bit line group including a first edge bit line;
- a second bit line group including a second edge bit line;
- and
- a first boundary transistor connected between the second edge bit line and a first global bit line connected to a bit line of the first bit line group, and configured to apply a non-selection voltage of the bit line of the first bit line group to the second edge bit line through the first global bit line when the first edge bit line is selected,
- wherein the first edge bit line is disposed closest to the second bit line group among the first bit line group, and the second edge bit line is disposed closest to the first bit line group among the second bit line group.
2 more elements
A resistive memory device comprising:
- a first bit line group including a first edge bit line;
- a second bit line group including a second edge bit line;
- a first edge transistor configured to apply a selection voltage to the first edge bit line according to a first selection signal;
- a second edge transistor configured to apply the selection voltage to the second edge bit line according to a second selection signal;
- a third edge transistor configured to apply a non-selection voltage to the first edge bit line according to the first selection signal;
- and
- a fourth edge transistor configured to apply the non-selection voltage to the second edge bit line according to the second selection signal,
- wherein the first selection signal is applied to a gate of the first edge transistor, one end of the first edge transistor is connected to a first global bit line of a plurality of global bit lines, and another end of the first edge transistor is connected to the first edge bit line,
- the second selection signal is applied to a gate of the second edge transistor, one end of the second edge transistor is connected to a second global bit line of the plurality of global bit lines, and another end of the second edge transistor is connected to the second edge bit line,
- the first selection signal is applied to a gate of the third edge transistor, one end of the third edge transistor is connected to the first edge bit line, and the non-selection voltage is applied to another end of the third edge transistor, and
- the second selection signal is applied to a gate of the fourth edge transistor, one end of the fourth edge transistor is connected to the second edge bit line, and the non-selection voltage is applied to another end of the fourth edge transistor.
8 more elements
Dependencies are inferred from the claim text.