Memory arrays with vertical thin film transistors coupled between digit lines
AssigneeMicron Technology, Inc.
InventorsScott J. Derner, Charles L. Ingalls
Life of this patent
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Abstract
In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.
Claims16
An apparatus comprising:
- a hierarchical digit line structure comprising a first digit line at a first level, a second digit line at a second level that is different from the first level, and a third digit line at the first level;
- a bus at the first level between the first digit line and the third digit line;
- a memory cell comprising a planar transistor and a storage element, the planar transistor comprising a source and drain arranged horizontally and coupled between the first digit line and the storage element;
- a vertical transistor comprising source and drain arranged vertically and coupled between the first and second digit lines;
- and
- a local sense amplifier coupled to the first and third digit lines and the bus, wherein the local sense amplifier comprises a plurality of vertical thin film transistors at a third level between the first and second levels.
An apparatus comprising:
- a hierarchical digit line structure comprising a first digit line at a first level and a second digit line at a second level that is different from the first level;
- a memory array comprising a first group of memory cells coupled to the first digit line at the first level, wherein the first group of memory cells comprise planar transistors and storage elements, and a second group of memory cells coupled to the second digit line at the first level, wherein the second group of memory cells comprise planar transistors and storage elements;
- and
- a local sense amplifier comprising:
- a first vertical thin film transistor at a third level between the first and second levels, and
- a second vertical thin film transistor at the third level.
A method of forming an apparatus, the method of forming comprising:
- forming a hierarchical digit line structure comprising a first digit line at a first level, a second digit line at a second level that is different from the first level, and a third digit line at the first level;
- forming a bus at the first level between the first digit line and the third digit line;
- forming a memory cell comprising a planar transistor and a storage element, the planar transistor comprising a source and drain arranged horizontally and coupled between the first digit line and the storage element;
- forming a vertical transistor comprising source and drain arranged vertically and coupled between the first and second digit lines;
- and
- forming a local sense amplifier coupled to the first and third digit lines and the bus, and wherein the local sense amplifier comprises a plurality of vertical thin film transistors at a third level between the first and second levels.
Dependencies are inferred from the claim text.