Memory device

A memory device, comprising:

• an input pad, configured to receive an input voltage;
• a first rank;
• a second rank;
• a first voltage detector, disposed in the first rank, coupled to the input pad, configured to receive the input voltage, and configured to transmit the input voltage to the first rank;
• a second voltage detector, disposed in the second rank, coupled to the first voltage detector through a first through-silicon via, and configured to receive the input voltage, and configured to transmit the input voltage to the second rank according to a control signal transmitted from the first voltage detector through the first voltage detector, so as to decide a state of the second rank, wherein the first rank and the second rank are located in different layers of the memory device, wherein the first rank is in an enable state;
• a first logic gate, coupled between the first voltage detector and the first rank;
• and
• a second logic gate, coupled between the second voltage detector and the second rank, and coupled to the first logic gate through a second through-silicon via, wherein the second logic gate is configured to receive a clock signal from the second through-silicon via to drive the second rank in an enable state.