Buried power rail structure for providing multi-domain power supply for memory device
AssigneeArm Limited
InventorsAndy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
Life of this patent
Estimating the term…
Abstract
Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.
Claims20
A device, comprising:
- memory circuitry having a bitcell array, wherein the bitcell array includes bitcells arranged in an array and header logic coupled to the bitcells;
- a frontside power network coupled to the bitcell array;
- a backside power network that provides power to the bitcell array;
- and
- transition vias that couple the backside power network to the frontside power network,
- wherein the backside power network provides power to the bitcell array by way of the transition vias being coupled to the frontside power network wherein the backside power network comprises a first backside power network, and wherein the first backside power network provides an external core voltage (VDDCE) to the header logic.
A device, comprising:
- memory circuitry having control logic;
- a backside power network that provides power to the control logic;
- and
- transition vias that couple the backside power network to the control logic,
- wherein the backside power network provides power to the control logic by way of the transition vias, wherein the control logic refers to input-output (I/O) control logic having sense amplifier logic and column multiplexer logic, wherein the backside power network comprises a first backside power network, and wherein the first backside power network is coupled directly to the sense amplifier logic.
A method, comprising:
- providing memory circuitry with a bitcell array and control logic;
- coupling a frontside power network to the bitcell array;
- coupling a backside power network to the frontside power network with transition vias;
- coupling the backside power network to the control logic with the transition vias, wherein
- the control logic refers to input-output (I/O) control logic having sense amplifier logic and column multiplexer logic;
- coupling the backside power network to the column multiplexer logic;
- and
- providing power from the backside power network to the bitcell array and the control logic of the memory circuitry.
Dependencies are inferred from the claim text.